1 #ifndef __LOCAL_POC_H__ 2 #define __LOCAL_POC_H__ 3 4 #define DRM_IOCTL_BASE 'd' 5 #define DRM_IOW(nr, type) _IOW(DRM_IOCTL_BASE, nr, type) 6 #define DRM_IOWR(nr, type) _IOWR(DRM_IOCTL_BASE, nr, type) 7 8 #define DRM_COMMAND_BASE 0x40 9 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000 10 11 /* reserved object handles when using deprecated object APIs - these 12 * are here so that libdrm can allow interoperability with the new 13 * object APIs 14 */ 15 #define NOUVEAU_ABI16_CLIENT 0xffffffff 16 #define NOUVEAU_ABI16_DEVICE 0xdddddddd 17 #define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 | (n)) 18 19 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 20 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 21 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 22 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 23 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 24 25 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 26 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 27 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 28 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 29 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 30 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 31 32 struct drm_nouveau_gem_info { 33 uint32_t handle; 34 uint32_t domain; 35 uint64_t size; 36 uint64_t offset; 37 uint64_t map_handle; 38 uint32_t tile_mode; 39 uint32_t tile_flags; 40 }; 41 42 struct drm_nouveau_gem_new { 43 struct drm_nouveau_gem_info info; 44 uint32_t channel_hint; 45 uint32_t align; 46 }; 47 48 struct drm_nouveau_gem_set_tiling { 49 uint32_t handle; 50 uint32_t tile_mode; 51 uint32_t tile_flags; 52 }; 53 54 #define NOUVEAU_GEM_MAX_BUFFERS 1024 55 struct drm_nouveau_gem_pushbuf_bo_presumed { 56 uint32_t valid; 57 uint32_t domain; 58 uint64_t offset; 59 }; 60 61 struct drm_nouveau_gem_pushbuf_bo { 62 uint64_t user_priv; 63 uint32_t handle; 64 uint32_t read_domains; 65 uint32_t write_domains; 66 uint32_t valid_domains; 67 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 68 }; 69 70 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 71 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 72 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 73 #define NOUVEAU_GEM_MAX_RELOCS 1024 74 struct drm_nouveau_gem_pushbuf_reloc { 75 uint32_t reloc_bo_index; 76 uint32_t reloc_bo_offset; 77 uint32_t bo_index; 78 uint32_t flags; 79 uint32_t data; 80 uint32_t vor; 81 uint32_t tor; 82 }; 83 84 #define NOUVEAU_GEM_MAX_PUSH 512 85 struct drm_nouveau_gem_pushbuf_push { 86 uint32_t bo_index; 87 uint32_t pad; 88 uint64_t offset; 89 uint64_t length; 90 }; 91 92 struct drm_nouveau_gem_pushbuf { 93 uint32_t channel; 94 uint32_t nr_buffers; 95 uint64_t buffers; 96 uint32_t nr_relocs; 97 uint32_t nr_push; 98 uint64_t relocs; 99 uint64_t push; 100 uint32_t suffix0; 101 uint32_t suffix1; 102 uint64_t vram_available; 103 uint64_t gart_available; 104 }; 105 106 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_WAIT 0x00000001 107 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_EMIT 0x00000002 108 struct drm_nouveau_gem_pushbuf_2 { 109 uint32_t channel; 110 uint32_t flags; 111 uint32_t nr_push; 112 uint32_t nr_buffers; 113 int32_t fence; /* in/out, depends on flags */ 114 uint32_t pad; 115 uint64_t push; /* in raw hw format */ 116 uint64_t buffers; /* ptr to drm_nouveau_gem_pushbuf_bo */ 117 uint64_t vram_available; 118 uint64_t gart_available; 119 }; 120 121 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 122 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 123 struct drm_nouveau_gem_cpu_prep { 124 uint32_t handle; 125 uint32_t flags; 126 }; 127 128 struct drm_nouveau_gem_cpu_fini { 129 uint32_t handle; 130 }; 131 132 struct drm_nouveau_gem_as_alloc { 133 uint64_t pages; /* in, page length */ 134 uint32_t page_size; /* in, byte page size */ 135 #define NOUVEAU_GEM_AS_SPARSE 0x1 136 uint32_t flags; 137 uint64_t align; /* in, requested alignment in bytes */ 138 uint64_t address; /* in/out, non-zero for fixed address allocation */ 139 }; 140 141 struct drm_nouveau_gem_as_free { 142 uint64_t address; /* in, byte address */ 143 }; 144 145 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8 146 #define NOUVEAU_GEM_CHANNEL_GR_ERROR_SW_NOTIFY 13 147 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31 148 #define NOUVEAU_GEM_CHANNEL_PBDMA_ERROR 32 149 struct drm_nouveau_gem_set_error_notifier { 150 uint32_t channel; 151 uint32_t buffer; 152 uint32_t offset; /* bytes, u32-aligned */ 153 }; 154 155 struct drm_nouveau_gem_map { 156 uint32_t handle; 157 uint32_t domain; 158 uint64_t offset; 159 uint64_t delta; 160 uint64_t length; 161 uint32_t tile_mode; 162 uint32_t tile_flags; 163 }; 164 165 struct drm_nouveau_gem_unmap { 166 uint32_t handle; 167 uint32_t pad; 168 uint64_t offset; 169 uint64_t delta; 170 uint64_t length; 171 }; 172 173 struct nvif_ioctl_v0 { 174 __u8 version; 175 #define NVIF_IOCTL_V0_OWNER_NVIF 0x00 176 #define NVIF_IOCTL_V0_OWNER_ANY 0xff 177 __u8 owner; 178 #define NVIF_IOCTL_V0_NOP 0x00 179 #define NVIF_IOCTL_V0_SCLASS 0x01 180 #define NVIF_IOCTL_V0_NEW 0x02 181 #define NVIF_IOCTL_V0_DEL 0x03 182 #define NVIF_IOCTL_V0_MTHD 0x04 183 #define NVIF_IOCTL_V0_RD 0x05 184 #define NVIF_IOCTL_V0_WR 0x06 185 #define NVIF_IOCTL_V0_MAP 0x07 186 #define NVIF_IOCTL_V0_UNMAP 0x08 187 #define NVIF_IOCTL_V0_NTFY_NEW 0x09 188 #define NVIF_IOCTL_V0_NTFY_DEL 0x0a 189 #define NVIF_IOCTL_V0_NTFY_GET 0x0b 190 #define NVIF_IOCTL_V0_NTFY_PUT 0x0c 191 __u8 type; 192 __u8 path_nr; 193 #define NVIF_IOCTL_V0_ROUTE_NVIF 0x00 194 #define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff 195 __u8 pad04[3]; 196 __u8 route; 197 __u64 token; 198 __u32 path[8]; /* in reverse */ 199 __u8 data[]; /* ioctl data (below) */ 200 }; 201 202 #define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */ 203 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ 204 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */ 205 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */ 206 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */ 207 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */ 208 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */ 209 #define DRM_NOUVEAU_NVIF 0x07 210 #define DRM_NOUVEAU_GEM_NEW 0x40 211 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 212 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 213 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 214 #define DRM_NOUVEAU_GEM_INFO 0x44 215 /* 216 * range (0x50+DRM_COMMAND_BASE)..DRM_COMMAND_END is reserved for staging, 217 * unstable ioctls 218 */ 219 #define DRM_NOUVEAU_STAGING_IOCTL 0x50 220 #define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0) 221 #define DRM_NOUVEAU_GEM_PUSHBUF_2 (DRM_NOUVEAU_STAGING_IOCTL + 0x1) 222 #define DRM_NOUVEAU_GEM_SET_INFO (DRM_NOUVEAU_STAGING_IOCTL + 0x2) 223 #define DRM_NOUVEAU_GEM_AS_ALLOC (DRM_NOUVEAU_STAGING_IOCTL + 0x3) 224 #define DRM_NOUVEAU_GEM_AS_FREE (DRM_NOUVEAU_STAGING_IOCTL + 0x4) 225 #define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER (DRM_NOUVEAU_STAGING_IOCTL + 0x5) 226 #define DRM_NOUVEAU_GEM_MAP (DRM_NOUVEAU_STAGING_IOCTL + 0x6) 227 #define DRM_NOUVEAU_GEM_UNMAP (DRM_NOUVEAU_STAGING_IOCTL + 0x7) 228 229 #define DRM_IOCTL_NOUVEAU_GEM_NEW \ 230 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 231 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF \ 232 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, \ 233 struct drm_nouveau_gem_pushbuf) 234 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP \ 235 DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, \ 236 struct drm_nouveau_gem_cpu_prep) 237 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI \ 238 DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, \ 239 struct drm_nouveau_gem_cpu_fini) 240 #define DRM_IOCTL_NOUVEAU_GEM_INFO \ 241 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 242 #define DRM_IOCTL_NOUVEAU_GEM_SET_TILING \ 243 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_TILING, \ 244 struct drm_nouveau_gem_set_tiling) 245 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF_2 \ 246 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF_2, \ 247 struct drm_nouveau_gem_pushbuf_2) 248 #define DRM_IOCTL_NOUVEAU_GEM_SET_INFO \ 249 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_INFO, \ 250 struct drm_nouveau_gem_info) 251 #define DRM_IOCTL_NOUVEAU_GEM_AS_ALLOC \ 252 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_AS_ALLOC, \ 253 struct drm_nouveau_gem_as_alloc) 254 #define DRM_IOCTL_NOUVEAU_GEM_AS_FREE \ 255 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_AS_FREE, \ 256 struct drm_nouveau_gem_as_free) 257 #define DRM_IOCTL_NOUVEAU_GEM_SET_ERROR_NOTIFIER \ 258 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER, \ 259 struct drm_nouveau_gem_set_error_notifier) 260 #define DRM_IOCTL_NOUVEAU_GEM_MAP \ 261 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_MAP, struct drm_nouveau_gem_map) 262 #define DRM_IOCTL_NOUVEAU_GEM_UNMAP \ 263 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_UNMAP, \ 264 struct drm_nouveau_gem_unmap) 265 266 #define DRM_IOCTL_NOUVEAU_NVIF \ 267 DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NVIF, struct nvif_ioctl_v0) 268 269 #endif 270
