1 /** 2 * Copyright (C) 2018 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions vand 14 * limitations under the License. 15 */ 16 #ifndef DRM_ENVIROMENT_H 17 #include <stdint.h> 18 #include <unistd.h> 19 20 enum drm_map_type { 21 _DRM_FRAME_BUFFER = 0, 22 _DRM_REGISTERS = 1, 23 _DRM_SHM = 2, 24 _DRM_AGP = 3, 25 _DRM_SCATTER_GATHER = 4, 26 _DRM_CONSISTENT = 5, 27 }; 28 29 enum drm_map_flags { 30 _DRM_RESTRICTED = 0x01, 31 _DRM_READ_ONLY = 0x02, 32 _DRM_LOCKED = 0x04, 33 _DRM_KERNEL = 0x08, 34 _DRM_WRITE_COMBINING = 0x10, 35 _DRM_CONTAINS_LOCK = 0x20, 36 _DRM_REMOVABLE = 0x40, 37 _DRM_DRIVER = 0x80 38 }; 39 40 enum host1x_class { 41 HOST1X_CLASS_HOST1X = 0x1, 42 HOST1X_CLASS_NVENC = 0x21, 43 HOST1X_CLASS_VI = 0x30, 44 HOST1X_CLASS_ISPA = 0x32, 45 HOST1X_CLASS_ISPB = 0x34, 46 HOST1X_CLASS_GR2D = 0x51, 47 HOST1X_CLASS_GR2D_SB = 0x52, 48 HOST1X_CLASS_VIC = 0x5D, 49 HOST1X_CLASS_GR3D = 0x60, 50 HOST1X_CLASS_NVJPG = 0xC0, 51 HOST1X_CLASS_NVDEC = 0xF0, 52 }; 53 54 struct drm_map { 55 unsigned long offset; 56 unsigned long size; 57 enum drm_map_type type; 58 enum drm_map_flags flags; 59 void* handle; 60 int mtrr; 61 }; 62 63 struct drm_version { 64 int version_major; 65 int version_minor; 66 int version_patchlevel; 67 size_t name_len; 68 char* name; 69 size_t date_len; 70 char* date; 71 size_t desc_len; 72 char* desc; 73 }; 74 75 struct drm_buf_desc { 76 int count; 77 int size; 78 int low_mark; 79 int high_mark; 80 enum { 81 _DRM_PAGE_ALIGN = 0x01, 82 _DRM_AGP_BUFFER = 0x02, 83 _DRM_SG_BUFFER = 0x04, 84 _DRM_FB_BUFFER = 0x08, 85 _DRM_PCI_BUFFER_RO = 0x10 86 } flags; 87 unsigned long agp_start; 88 }; 89 90 struct drm_buf_info { 91 int count; 92 struct drm_buf_desc* list; 93 }; 94 95 struct drm_buf_free { 96 int count; 97 int* list; 98 }; 99 100 struct drm_nouveau_gem_info { 101 uint32_t handle; 102 uint32_t domain; 103 uint64_t size; 104 uint64_t offset; 105 uint64_t map_handle; 106 uint32_t tile_mode; 107 uint32_t tile_flags; 108 }; 109 110 struct drm_nouveau_gem_map { 111 uint32_t handle; 112 uint32_t domain; 113 uint64_t offset; 114 uint64_t delta; 115 uint64_t length; 116 uint32_t tile_mode; 117 uint32_t tile_flags; 118 }; 119 120 struct drm_nouveau_gem_unmap { 121 uint32_t handle; 122 uint32_t pad; 123 uint64_t offset; 124 uint64_t delta; 125 uint64_t length; 126 }; 127 128 struct drm_nouveau_gem_new { 129 struct drm_nouveau_gem_info info; 130 uint32_t channel_hint; 131 uint32_t align; 132 }; 133 134 struct drm_nouveau_gem_pushbuf { 135 uint32_t channel; 136 uint32_t nr_buffers; 137 uint64_t buffers; 138 uint32_t nr_relocs; 139 uint32_t nr_push; 140 uint64_t relocs; 141 uint64_t push; 142 uint32_t suffix0; 143 uint32_t suffix1; 144 uint64_t vram_available; 145 uint64_t gart_available; 146 }; 147 148 struct drm_nouveau_gem_pushbuf_bo_presumed { 149 uint32_t valid; 150 uint32_t domain; 151 uint64_t offset; 152 }; 153 struct drm_nouveau_gem_pushbuf_bo { 154 uint64_t user_priv; 155 uint32_t handle; 156 uint32_t read_domains; 157 uint32_t write_domains; 158 uint32_t valid_domains; 159 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 160 }; 161 162 struct drm_nouveau_channel_alloc { 163 uint32_t fb_ctxdma_handle; 164 uint32_t tt_ctxdma_handle; 165 int channel; 166 uint32_t pushbuf_domains; 167 uint32_t notifier_handle; 168 struct { 169 uint32_t handle; 170 uint32_t grclass; 171 } subchan[8]; 172 uint32_t nr_subchan; 173 }; 174 175 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 176 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 177 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 178 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 179 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 180 181 #define DRM_COMMAND_BASE 0x40 182 #define DRM_COMMAND_END 0xA0 183 184 #define DRM_NOUVEAU_GETPARAM 0x00 185 #define DRM_NOUVEAU_SETPARAM 0x01 186 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 187 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 188 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 189 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 190 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 191 #define DRM_NOUVEAU_NVIF 0x07 192 #define DRM_NOUVEAU_GEM_NEW 0x40 193 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 194 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 195 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 196 #define DRM_NOUVEAU_GEM_INFO 0x44 197 #define DRM_NOUVEAU_STAGING_IOCTL 0x50 198 #define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0) 199 #define DRM_NOUVEAU_GEM_PUSHBUF_2 (DRM_NOUVEAU_STAGING_IOCTL + 0x1) 200 #define DRM_NOUVEAU_GEM_SET_INFO (DRM_NOUVEAU_STAGING_IOCTL + 0x2) 201 #define DRM_NOUVEAU_GEM_AS_ALLOC (DRM_NOUVEAU_STAGING_IOCTL + 0x3) 202 #define DRM_NOUVEAU_GEM_AS_FREE (DRM_NOUVEAU_STAGING_IOCTL + 0x4) 203 #define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER (DRM_NOUVEAU_STAGING_IOCTL + 0x5) 204 #define DRM_NOUVEAU_GEM_MAP (DRM_NOUVEAU_STAGING_IOCTL + 0x6) 205 #define DRM_NOUVEAU_GEM_UNMAP (DRM_NOUVEAU_STAGING_IOCTL + 0x7) 206 207 #define DRM_IOCTL_BASE 'd' 208 #define DRM_IOR(nr, type) _IOR(DRM_IOCTL_BASE, nr, type) 209 #define DRM_IOW(nr, type) _IOW(DRM_IOCTL_BASE, nr, type) 210 #define DRM_IOWR(nr, type) _IOWR(DRM_IOCTL_BASE, nr, type) 211 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 212 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 213 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 214 #define DRM_IOCTL_FREE_BUFS DRM_IOW(0x1a, struct drm_buf_free) 215 216 #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) 217 #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) 218 #define DRM_IOCTL_NOUVEAU_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_MAP, struct drm_nouveau_gem_map) 219 #define DRM_IOCTL_NOUVEAU_GEM_UNMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_UNMAP, struct drm_nouveau_gem_unmap) 220 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) 221 #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) 222 223 #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) 224 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) 225 226 struct drm_tegra_gem_create { 227 __u64 size; 228 __u32 flags; 229 __u32 handle; 230 }; 231 232 struct drm_tegra_gem_mmap { 233 __u32 handle; 234 __u32 offset; 235 }; 236 237 struct drm_tegra_syncpt_read { 238 __u32 id; 239 __u32 value; 240 }; 241 242 struct drm_tegra_syncpt_incr { 243 __u32 id; 244 __u32 pad; 245 }; 246 247 struct drm_tegra_syncpt_wait { 248 __u32 id; 249 __u32 thresh; 250 __u32 timeout; 251 __u32 value; 252 }; 253 254 #define DRM_TEGRA_NO_TIMEOUT (0xffffffff) 255 256 struct drm_tegra_open_channel { 257 __u32 client; 258 __u32 pad; 259 __u64 context; 260 }; 261 262 struct drm_tegra_close_channel { 263 __u64 context; 264 }; 265 266 struct drm_tegra_get_syncpt { 267 __u64 context; 268 __u32 index; 269 __u32 id; 270 }; 271 272 struct drm_tegra_get_syncpt_base { 273 __u64 context; 274 __u32 syncpt; 275 __u32 id; 276 }; 277 278 struct drm_tegra_syncpt { 279 __u32 id; 280 __u32 incrs; 281 }; 282 283 struct drm_tegra_cmdbuf { 284 __u32 handle; 285 __u32 offset; 286 __u32 words; 287 __u32 pad; 288 }; 289 290 struct drm_tegra_reloc { 291 struct { 292 __u32 handle; 293 __u32 offset; 294 } cmdbuf; 295 struct { 296 __u32 handle; 297 __u32 offset; 298 } target; 299 __u32 shift; 300 __u32 pad; 301 }; 302 303 struct drm_tegra_waitchk { 304 __u32 handle; 305 __u32 offset; 306 __u32 syncpt; 307 __u32 thresh; 308 }; 309 310 struct drm_tegra_submit { 311 __u64 context; 312 __u32 num_syncpts; 313 __u32 num_cmdbufs; 314 __u32 num_relocs; 315 __u32 num_waitchks; 316 __u32 waitchk_mask; 317 __u32 timeout; 318 __u64 syncpts; 319 __u64 cmdbufs; 320 __u64 relocs; 321 __u64 waitchks; 322 __u32 fence; 323 __u32 reserved0; 324 __u64 fences; 325 326 __u32 reserved1[2]; 327 }; 328 329 #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 330 #define DRM_TEGRA_GEM_TILING_MODE_TILED 1 331 #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 332 333 struct drm_tegra_gem_set_tiling { 334 __u32 handle; 335 __u32 mode; 336 __u32 value; 337 __u32 pad; 338 }; 339 340 struct drm_tegra_gem_get_tiling { 341 __u32 handle; 342 __u32 mode; 343 __u32 value; 344 __u32 pad; 345 }; 346 347 #define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) 348 #define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) 349 350 struct drm_tegra_gem_set_flags { 351 __u32 handle; 352 __u32 flags; 353 }; 354 355 struct drm_tegra_gem_get_flags { 356 __u32 handle; 357 __u32 flags; 358 }; 359 360 enum request_type { 361 DRM_TEGRA_REQ_TYPE_CLK_HZ = 0, 362 DRM_TEGRA_REQ_TYPE_BW_KBPS, 363 }; 364 365 struct drm_tegra_get_clk_rate { 366 __u32 id; 367 __u32 type; 368 __u64 data; 369 }; 370 371 struct drm_tegra_set_clk_rate { 372 __u32 id; 373 __u32 type; 374 __u64 data; 375 }; 376 377 struct drm_tegra_constraint { 378 __u64 context; 379 __u32 index; 380 __u32 type; 381 __u32 rate; 382 __u32 pad; 383 }; 384 385 struct drm_tegra_keepon { 386 __u64 context; 387 }; 388 389 #define DRM_TEGRA_GEM_CREATE 0x00 390 #define DRM_TEGRA_GEM_MMAP 0x01 391 #define DRM_TEGRA_SYNCPT_READ 0x02 392 #define DRM_TEGRA_SYNCPT_INCR 0x03 393 #define DRM_TEGRA_SYNCPT_WAIT 0x04 394 #define DRM_TEGRA_OPEN_CHANNEL 0x05 395 #define DRM_TEGRA_CLOSE_CHANNEL 0x06 396 #define DRM_TEGRA_GET_SYNCPT 0x07 397 #define DRM_TEGRA_SUBMIT 0x08 398 #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 399 #define DRM_TEGRA_GEM_SET_TILING 0x0a 400 #define DRM_TEGRA_GEM_GET_TILING 0x0b 401 #define DRM_TEGRA_GEM_SET_FLAGS 0x0c 402 #define DRM_TEGRA_GEM_GET_FLAGS 0x0d 403 #define DRM_TEGRA_GET_CLK_RATE 0x0e 404 #define DRM_TEGRA_SET_CLK_RATE 0x0f 405 #define DRM_TEGRA_START_KEEPON 0x10 406 #define DRM_TEGRA_STOP_KEEPON 0x11 407 #define DRM_TEGRA_GET_CLK_CONSTRAINT 0x12 408 #define DRM_TEGRA_SET_CLK_CONSTRAINT 0x13 409 410 #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) 411 #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) 412 #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) 413 #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) 414 #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) 415 #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) 416 #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel) 417 #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) 418 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) 419 #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) 420 #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) 421 #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) 422 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) 423 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) 424 #define DRM_IOCTL_TEGRA_GET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_CLK_RATE, struct drm_tegra_get_clk_rate) 425 #define DRM_IOCTL_TEGRA_SET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SET_CLK_RATE, struct drm_tegra_set_clk_rate) 426 #define DRM_IOCTL_TEGRA_START_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_START_KEEPON, struct drm_tegra_keepon) 427 #define DRM_IOCTL_TEGRA_STOP_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_STOP_KEEPON, struct drm_tegra_keepon) 428 #define DRM_IOCTL_TEGRA_GET_CLK_CONSTRAINT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_CLK_CONSTRAINT, struct drm_tegra_constraint) 429 #define DRM_IOCTL_TEGRA_SET_CLK_CONSTRAINT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SET_CLK_CONSTRAINT, struct drm_tegra_constraint) 430 431 #endif 432
