1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _MSM_DRM_PP_H_ 20 #define _MSM_DRM_PP_H_ 21 #include <linux/types.h> 22 struct drm_msm_pcc_coeff { 23 __u32 c; 24 __u32 r; 25 __u32 g; 26 __u32 b; 27 __u32 rg; 28 __u32 gb; 29 __u32 rb; 30 __u32 rgb; 31 }; 32 #define DRM_MSM_PCC3 33 struct drm_msm_pcc { 34 __u64 flags; 35 struct drm_msm_pcc_coeff r; 36 struct drm_msm_pcc_coeff g; 37 struct drm_msm_pcc_coeff b; 38 __u32 r_rr; 39 __u32 r_gg; 40 __u32 r_bb; 41 __u32 g_rr; 42 __u32 g_gg; 43 __u32 g_bb; 44 __u32 b_rr; 45 __u32 b_gg; 46 __u32 b_bb; 47 }; 48 #define PA_VLUT_SIZE 256 49 struct drm_msm_pa_vlut { 50 __u64 flags; 51 __u32 val[PA_VLUT_SIZE]; 52 }; 53 #define PA_HSIC_HUE_ENABLE (1 << 0) 54 #define PA_HSIC_SAT_ENABLE (1 << 1) 55 #define PA_HSIC_VAL_ENABLE (1 << 2) 56 #define PA_HSIC_CONT_ENABLE (1 << 3) 57 #define DRM_MSM_PA_HSIC 58 struct drm_msm_pa_hsic { 59 __u64 flags; 60 __u32 hue; 61 __u32 saturation; 62 __u32 value; 63 __u32 contrast; 64 }; 65 #define MEMCOL_PROT_HUE (1 << 0) 66 #define MEMCOL_PROT_SAT (1 << 1) 67 #define MEMCOL_PROT_VAL (1 << 2) 68 #define MEMCOL_PROT_CONT (1 << 3) 69 #define MEMCOL_PROT_SIXZONE (1 << 4) 70 #define MEMCOL_PROT_BLEND (1 << 5) 71 #define DRM_MSM_MEMCOL 72 struct drm_msm_memcol { 73 __u64 prot_flags; 74 __u32 color_adjust_p0; 75 __u32 color_adjust_p1; 76 __u32 color_adjust_p2; 77 __u32 blend_gain; 78 __u32 sat_hold; 79 __u32 val_hold; 80 __u32 hue_region; 81 __u32 sat_region; 82 __u32 val_region; 83 }; 84 #define DRM_MSM_SIXZONE 85 #define SIXZONE_LUT_SIZE 384 86 #define SIXZONE_HUE_ENABLE (1 << 0) 87 #define SIXZONE_SAT_ENABLE (1 << 1) 88 #define SIXZONE_VAL_ENABLE (1 << 2) 89 struct drm_msm_sixzone_curve { 90 __u32 p1; 91 __u32 p0; 92 }; 93 struct drm_msm_sixzone { 94 __u64 flags; 95 __u32 threshold; 96 __u32 adjust_p0; 97 __u32 adjust_p1; 98 __u32 sat_hold; 99 __u32 val_hold; 100 struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE]; 101 }; 102 #define GAMUT_3D_MODE_17 1 103 #define GAMUT_3D_MODE_5 2 104 #define GAMUT_3D_MODE_13 3 105 #define GAMUT_3D_MODE17_TBL_SZ 1229 106 #define GAMUT_3D_MODE5_TBL_SZ 32 107 #define GAMUT_3D_MODE13_TBL_SZ 550 108 #define GAMUT_3D_SCALE_OFF_SZ 16 109 #define GAMUT_3D_SCALEB_OFF_SZ 12 110 #define GAMUT_3D_TBL_NUM 4 111 #define GAMUT_3D_SCALE_OFF_TBL_NUM 3 112 #define GAMUT_3D_MAP_EN (1 << 0) 113 struct drm_msm_3d_col { 114 __u32 c2_c1; 115 __u32 c0; 116 }; 117 struct drm_msm_3d_gamut { 118 __u64 flags; 119 __u32 mode; 120 __u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ]; 121 struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ]; 122 }; 123 #define PGC_TBL_LEN 512 124 #define PGC_8B_ROUND (1 << 0) 125 struct drm_msm_pgc_lut { 126 __u64 flags; 127 __u32 c0[PGC_TBL_LEN]; 128 __u32 c1[PGC_TBL_LEN]; 129 __u32 c2[PGC_TBL_LEN]; 130 }; 131 #define IGC_TBL_LEN 256 132 #define IGC_DITHER_ENABLE (1 << 0) 133 struct drm_msm_igc_lut { 134 __u64 flags; 135 __u32 c0[IGC_TBL_LEN]; 136 __u32 c1[IGC_TBL_LEN]; 137 __u32 c2[IGC_TBL_LEN]; 138 __u32 strength; 139 }; 140 #define HIST_V_SIZE 256 141 struct drm_msm_hist { 142 __u64 flags; 143 __u32 data[HIST_V_SIZE]; 144 }; 145 #define AD4_LUT_GRP0_SIZE 33 146 #define AD4_LUT_GRP1_SIZE 32 147 struct drm_msm_ad4_init { 148 __u32 init_param_001[AD4_LUT_GRP0_SIZE]; 149 __u32 init_param_002[AD4_LUT_GRP0_SIZE]; 150 __u32 init_param_003[AD4_LUT_GRP0_SIZE]; 151 __u32 init_param_004[AD4_LUT_GRP0_SIZE]; 152 __u32 init_param_005[AD4_LUT_GRP1_SIZE]; 153 __u32 init_param_006[AD4_LUT_GRP1_SIZE]; 154 __u32 init_param_007[AD4_LUT_GRP0_SIZE]; 155 __u32 init_param_008[AD4_LUT_GRP0_SIZE]; 156 __u32 init_param_009; 157 __u32 init_param_010; 158 __u32 init_param_011; 159 __u32 init_param_012; 160 __u32 init_param_013; 161 __u32 init_param_014; 162 __u32 init_param_015; 163 __u32 init_param_016; 164 __u32 init_param_017; 165 __u32 init_param_018; 166 __u32 init_param_019; 167 __u32 init_param_020; 168 __u32 init_param_021; 169 __u32 init_param_022; 170 __u32 init_param_023; 171 __u32 init_param_024; 172 __u32 init_param_025; 173 __u32 init_param_026; 174 __u32 init_param_027; 175 __u32 init_param_028; 176 __u32 init_param_029; 177 __u32 init_param_030; 178 __u32 init_param_031; 179 __u32 init_param_032; 180 __u32 init_param_033; 181 __u32 init_param_034; 182 __u32 init_param_035; 183 __u32 init_param_036; 184 __u32 init_param_037; 185 __u32 init_param_038; 186 __u32 init_param_039; 187 __u32 init_param_040; 188 __u32 init_param_041; 189 __u32 init_param_042; 190 __u32 init_param_043; 191 __u32 init_param_044; 192 __u32 init_param_045; 193 __u32 init_param_046; 194 __u32 init_param_047; 195 __u32 init_param_048; 196 __u32 init_param_049; 197 __u32 init_param_050; 198 __u32 init_param_051; 199 __u32 init_param_052; 200 __u32 init_param_053; 201 __u32 init_param_054; 202 __u32 init_param_055; 203 __u32 init_param_056; 204 __u32 init_param_057; 205 __u32 init_param_058; 206 __u32 init_param_059; 207 __u32 init_param_060; 208 __u32 init_param_061; 209 __u32 init_param_062; 210 __u32 init_param_063; 211 __u32 init_param_064; 212 __u32 init_param_065; 213 __u32 init_param_066; 214 __u32 init_param_067; 215 __u32 init_param_068; 216 __u32 init_param_069; 217 __u32 init_param_070; 218 __u32 init_param_071; 219 __u32 init_param_072; 220 __u32 init_param_073; 221 __u32 init_param_074; 222 __u32 init_param_075; 223 }; 224 struct drm_msm_ad4_cfg { 225 __u32 cfg_param_001; 226 __u32 cfg_param_002; 227 __u32 cfg_param_003; 228 __u32 cfg_param_004; 229 __u32 cfg_param_005; 230 __u32 cfg_param_006; 231 __u32 cfg_param_007; 232 __u32 cfg_param_008; 233 __u32 cfg_param_009; 234 __u32 cfg_param_010; 235 __u32 cfg_param_011; 236 __u32 cfg_param_012; 237 __u32 cfg_param_013; 238 __u32 cfg_param_014; 239 __u32 cfg_param_015; 240 __u32 cfg_param_016; 241 __u32 cfg_param_017; 242 __u32 cfg_param_018; 243 __u32 cfg_param_019; 244 __u32 cfg_param_020; 245 __u32 cfg_param_021; 246 __u32 cfg_param_022; 247 __u32 cfg_param_023; 248 __u32 cfg_param_024; 249 __u32 cfg_param_025; 250 __u32 cfg_param_026; 251 __u32 cfg_param_027; 252 __u32 cfg_param_028; 253 __u32 cfg_param_029; 254 __u32 cfg_param_030; 255 __u32 cfg_param_031; 256 __u32 cfg_param_032; 257 __u32 cfg_param_033; 258 __u32 cfg_param_034; 259 __u32 cfg_param_035; 260 __u32 cfg_param_036; 261 __u32 cfg_param_037; 262 __u32 cfg_param_038; 263 __u32 cfg_param_039; 264 __u32 cfg_param_040; 265 __u32 cfg_param_041; 266 __u32 cfg_param_042; 267 __u32 cfg_param_043; 268 __u32 cfg_param_044; 269 __u32 cfg_param_045; 270 __u32 cfg_param_046; 271 __u32 cfg_param_047; 272 __u32 cfg_param_048; 273 __u32 cfg_param_049; 274 __u32 cfg_param_050; 275 __u32 cfg_param_051; 276 __u32 cfg_param_052; 277 __u32 cfg_param_053; 278 }; 279 #define DITHER_MATRIX_SZ 16 280 struct drm_msm_dither { 281 __u64 flags; 282 __u32 temporal_en; 283 __u32 c0_bitdepth; 284 __u32 c1_bitdepth; 285 __u32 c2_bitdepth; 286 __u32 c3_bitdepth; 287 __u32 matrix[DITHER_MATRIX_SZ]; 288 }; 289 #define DRM_MSM_PA_DITHER 290 struct drm_msm_pa_dither { 291 __u64 flags; 292 __u32 strength; 293 __u32 offset_en; 294 __u32 matrix[DITHER_MATRIX_SZ]; 295 }; 296 #endif 297 298
