1 #ifndef _MSM_DRM_PP_H_ 2 #define _MSM_DRM_PP_H_ 3 4 #include <linux/types.h> 5 /** 6 * struct drm_msm_pcc_coeff - PCC coefficient structure for each color 7 * component. 8 * @c: constant coefficient. 9 * @r: red coefficient. 10 * @g: green coefficient. 11 * @b: blue coefficient. 12 * @rg: red green coefficient. 13 * @gb: green blue coefficient. 14 * @rb: red blue coefficient. 15 * @rgb: red blue green coefficient. 16 */ 17 18 struct drm_msm_pcc_coeff { 19 __u32 c; 20 __u32 r; 21 __u32 g; 22 __u32 b; 23 __u32 rg; 24 __u32 gb; 25 __u32 rb; 26 __u32 rgb; 27 }; 28 29 /** 30 * struct drm_msm_pcc - pcc feature structure 31 * @flags: for customizing operations 32 * @r: red coefficients. 33 * @g: green coefficients. 34 * @b: blue coefficients. 35 * @r_rr: second order coefficients 36 * @r_gg: second order coefficients 37 * @r_bb: second order coefficients 38 * @g_rr: second order coefficients 39 * @g_gg: second order coefficients 40 * @g_bb: second order coefficients 41 * @b_rr: second order coefficients 42 * @b_gg: second order coefficients 43 * @b_bb: second order coefficients 44 */ 45 #define DRM_MSM_PCC3 46 struct drm_msm_pcc { 47 __u64 flags; 48 struct drm_msm_pcc_coeff r; 49 struct drm_msm_pcc_coeff g; 50 struct drm_msm_pcc_coeff b; 51 __u32 r_rr; 52 __u32 r_gg; 53 __u32 r_bb; 54 __u32 g_rr; 55 __u32 g_gg; 56 __u32 g_bb; 57 __u32 b_rr; 58 __u32 b_gg; 59 __u32 b_bb; 60 }; 61 62 /* struct drm_msm_pa_vlut - picture adjustment vLUT structure 63 * flags: for customizing vlut operation 64 * val: vLUT values 65 */ 66 #define PA_VLUT_SIZE 256 67 struct drm_msm_pa_vlut { 68 __u64 flags; 69 __u32 val[PA_VLUT_SIZE]; 70 }; 71 72 #define PA_HSIC_HUE_ENABLE (1 << 0) 73 #define PA_HSIC_SAT_ENABLE (1 << 1) 74 #define PA_HSIC_VAL_ENABLE (1 << 2) 75 #define PA_HSIC_CONT_ENABLE (1 << 3) 76 /** 77 * struct drm_msm_pa_hsic - pa hsic feature structure 78 * @flags: flags for the feature customization, values can be: 79 * - PA_HSIC_HUE_ENABLE: Enable hue adjustment 80 * - PA_HSIC_SAT_ENABLE: Enable saturation adjustment 81 * - PA_HSIC_VAL_ENABLE: Enable value adjustment 82 * - PA_HSIC_CONT_ENABLE: Enable contrast adjustment 83 * 84 * @hue: hue setting 85 * @saturation: saturation setting 86 * @value: value setting 87 * @contrast: contrast setting 88 */ 89 #define DRM_MSM_PA_HSIC 90 struct drm_msm_pa_hsic { 91 __u64 flags; 92 __u32 hue; 93 __u32 saturation; 94 __u32 value; 95 __u32 contrast; 96 }; 97 98 #define MEMCOL_PROT_HUE (1 << 0) 99 #define MEMCOL_PROT_SAT (1 << 1) 100 #define MEMCOL_PROT_VAL (1 << 2) 101 #define MEMCOL_PROT_CONT (1 << 3) 102 #define MEMCOL_PROT_SIXZONE (1 << 4) 103 #define MEMCOL_PROT_BLEND (1 << 5) 104 /* struct drm_msm_memcol - Memory color feature structure. 105 * Skin, sky, foliage features are supported. 106 * @prot_flags: Bit mask for enabling protection feature. 107 * @color_adjust_p0: Adjustment curve. 108 * @color_adjust_p1: Adjustment curve. 109 * @color_adjust_p2: Adjustment curve. 110 * @blend_gain: Blend gain weightage from othe PA features. 111 * @sat_hold: Saturation hold value. 112 * @val_hold: Value hold info. 113 * @hue_region: Hue qualifier. 114 * @sat_region: Saturation qualifier. 115 * @val_region: Value qualifier. 116 */ 117 #define DRM_MSM_MEMCOL 118 struct drm_msm_memcol { 119 __u64 prot_flags; 120 __u32 color_adjust_p0; 121 __u32 color_adjust_p1; 122 __u32 color_adjust_p2; 123 __u32 blend_gain; 124 __u32 sat_hold; 125 __u32 val_hold; 126 __u32 hue_region; 127 __u32 sat_region; 128 __u32 val_region; 129 }; 130 131 #define DRM_MSM_SIXZONE 132 #define SIXZONE_LUT_SIZE 384 133 #define SIXZONE_HUE_ENABLE (1 << 0) 134 #define SIXZONE_SAT_ENABLE (1 << 1) 135 #define SIXZONE_VAL_ENABLE (1 << 2) 136 /* struct drm_msm_sixzone_curve - Sixzone HSV adjustment curve structure. 137 * @p0: Hue adjustment. 138 * @p1: Saturation/Value adjustment. 139 */ 140 struct drm_msm_sixzone_curve { 141 __u32 p1; 142 __u32 p0; 143 }; 144 145 /* struct drm_msm_sixzone - Sixzone feature structure. 146 * @flags: for feature customization, values can be: 147 * - SIXZONE_HUE_ENABLE: Enable hue adjustment 148 * - SIXZONE_SAT_ENABLE: Enable saturation adjustment 149 * - SIXZONE_VAL_ENABLE: Enable value adjustment 150 * @threshold: threshold qualifier. 151 * @adjust_p0: Adjustment curve. 152 * @adjust_p1: Adjustment curve. 153 * @sat_hold: Saturation hold info. 154 * @val_hold: Value hold info. 155 * @curve: HSV adjustment curve lut. 156 */ 157 struct drm_msm_sixzone { 158 __u64 flags; 159 __u32 threshold; 160 __u32 adjust_p0; 161 __u32 adjust_p1; 162 __u32 sat_hold; 163 __u32 val_hold; 164 struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE]; 165 }; 166 167 #define GAMUT_3D_MODE_17 1 168 #define GAMUT_3D_MODE_5 2 169 #define GAMUT_3D_MODE_13 3 170 171 #define GAMUT_3D_MODE17_TBL_SZ 1229 172 #define GAMUT_3D_MODE5_TBL_SZ 32 173 #define GAMUT_3D_MODE13_TBL_SZ 550 174 #define GAMUT_3D_SCALE_OFF_SZ 16 175 #define GAMUT_3D_SCALEB_OFF_SZ 12 176 #define GAMUT_3D_TBL_NUM 4 177 #define GAMUT_3D_SCALE_OFF_TBL_NUM 3 178 #define GAMUT_3D_MAP_EN (1 << 0) 179 180 /** 181 * struct drm_msm_3d_col - 3d gamut color component structure 182 * @c0: Holds c0 value 183 * @c2_c1: Holds c2/c1 values 184 */ 185 struct drm_msm_3d_col { 186 __u32 c2_c1; 187 __u32 c0; 188 }; 189 /** 190 * struct drm_msm_3d_gamut - 3d gamut feature structure 191 * @flags: flags for the feature values are: 192 * 0 - no map 193 * GAMUT_3D_MAP_EN - enable map 194 * @mode: lut mode can take following values: 195 * - GAMUT_3D_MODE_17 196 * - GAMUT_3D_MODE_5 197 * - GAMUT_3D_MODE_13 198 * @scale_off: Scale offset table 199 * @col: Color component tables 200 */ 201 struct drm_msm_3d_gamut { 202 __u64 flags; 203 __u32 mode; 204 __u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ]; 205 struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ]; 206 }; 207 208 #define PGC_TBL_LEN 512 209 #define PGC_8B_ROUND (1 << 0) 210 /** 211 * struct drm_msm_pgc_lut - pgc lut feature structure 212 * @flags: flags for the featue values can be: 213 * - PGC_8B_ROUND 214 * @c0: color0 component lut 215 * @c1: color1 component lut 216 * @c2: color2 component lut 217 */ 218 struct drm_msm_pgc_lut { 219 __u64 flags; 220 __u32 c0[PGC_TBL_LEN]; 221 __u32 c1[PGC_TBL_LEN]; 222 __u32 c2[PGC_TBL_LEN]; 223 }; 224 225 #define IGC_TBL_LEN 256 226 #define IGC_DITHER_ENABLE (1 << 0) 227 /** 228 * struct drm_msm_igc_lut - igc lut feature structure 229 * @flags: flags for the feature customization, values can be: 230 * - IGC_DITHER_ENABLE: Enable dither functionality 231 * @c0: color0 component lut 232 * @c1: color1 component lut 233 * @c2: color2 component lut 234 * @strength: dither strength, considered valid when IGC_DITHER_ENABLE 235 * is set in flags. Strength value based on source bit width. 236 */ 237 struct drm_msm_igc_lut { 238 __u64 flags; 239 __u32 c0[IGC_TBL_LEN]; 240 __u32 c1[IGC_TBL_LEN]; 241 __u32 c2[IGC_TBL_LEN]; 242 __u32 strength; 243 }; 244 245 #define HIST_V_SIZE 256 246 /** 247 * struct drm_msm_hist - histogram feature structure 248 * @flags: for customizing operations 249 * @data: histogram data 250 */ 251 struct drm_msm_hist { 252 __u64 flags; 253 __u32 data[HIST_V_SIZE]; 254 }; 255 256 #define AD4_LUT_GRP0_SIZE 33 257 #define AD4_LUT_GRP1_SIZE 32 258 /* 259 * struct drm_msm_ad4_init - ad4 init structure set by user-space client. 260 * Init param values can change based on tuning 261 * hence it is passed by user-space clients. 262 */ 263 struct drm_msm_ad4_init { 264 __u32 init_param_001[AD4_LUT_GRP0_SIZE]; 265 __u32 init_param_002[AD4_LUT_GRP0_SIZE]; 266 __u32 init_param_003[AD4_LUT_GRP0_SIZE]; 267 __u32 init_param_004[AD4_LUT_GRP0_SIZE]; 268 __u32 init_param_005[AD4_LUT_GRP1_SIZE]; 269 __u32 init_param_006[AD4_LUT_GRP1_SIZE]; 270 __u32 init_param_007[AD4_LUT_GRP0_SIZE]; 271 __u32 init_param_008[AD4_LUT_GRP0_SIZE]; 272 __u32 init_param_009; 273 __u32 init_param_010; 274 __u32 init_param_011; 275 __u32 init_param_012; 276 __u32 init_param_013; 277 __u32 init_param_014; 278 __u32 init_param_015; 279 __u32 init_param_016; 280 __u32 init_param_017; 281 __u32 init_param_018; 282 __u32 init_param_019; 283 __u32 init_param_020; 284 __u32 init_param_021; 285 __u32 init_param_022; 286 __u32 init_param_023; 287 __u32 init_param_024; 288 __u32 init_param_025; 289 __u32 init_param_026; 290 __u32 init_param_027; 291 __u32 init_param_028; 292 __u32 init_param_029; 293 __u32 init_param_030; 294 __u32 init_param_031; 295 __u32 init_param_032; 296 __u32 init_param_033; 297 __u32 init_param_034; 298 __u32 init_param_035; 299 __u32 init_param_036; 300 __u32 init_param_037; 301 __u32 init_param_038; 302 __u32 init_param_039; 303 __u32 init_param_040; 304 __u32 init_param_041; 305 __u32 init_param_042; 306 __u32 init_param_043; 307 __u32 init_param_044; 308 __u32 init_param_045; 309 __u32 init_param_046; 310 __u32 init_param_047; 311 __u32 init_param_048; 312 __u32 init_param_049; 313 __u32 init_param_050; 314 __u32 init_param_051; 315 __u32 init_param_052; 316 __u32 init_param_053; 317 __u32 init_param_054; 318 __u32 init_param_055; 319 __u32 init_param_056; 320 __u32 init_param_057; 321 __u32 init_param_058; 322 __u32 init_param_059; 323 __u32 init_param_060; 324 __u32 init_param_061; 325 __u32 init_param_062; 326 __u32 init_param_063; 327 __u32 init_param_064; 328 __u32 init_param_065; 329 __u32 init_param_066; 330 __u32 init_param_067; 331 __u32 init_param_068; 332 __u32 init_param_069; 333 __u32 init_param_070; 334 __u32 init_param_071; 335 __u32 init_param_072; 336 __u32 init_param_073; 337 __u32 init_param_074; 338 __u32 init_param_075; 339 }; 340 341 /* 342 * struct drm_msm_ad4_cfg - ad4 config structure set by user-space client. 343 * Config param values can vary based on tuning, 344 * hence it is passed by user-space clients. 345 */ 346 struct drm_msm_ad4_cfg { 347 __u32 cfg_param_001; 348 __u32 cfg_param_002; 349 __u32 cfg_param_003; 350 __u32 cfg_param_004; 351 __u32 cfg_param_005; 352 __u32 cfg_param_006; 353 __u32 cfg_param_007; 354 __u32 cfg_param_008; 355 __u32 cfg_param_009; 356 __u32 cfg_param_010; 357 __u32 cfg_param_011; 358 __u32 cfg_param_012; 359 __u32 cfg_param_013; 360 __u32 cfg_param_014; 361 __u32 cfg_param_015; 362 __u32 cfg_param_016; 363 __u32 cfg_param_017; 364 __u32 cfg_param_018; 365 __u32 cfg_param_019; 366 __u32 cfg_param_020; 367 __u32 cfg_param_021; 368 __u32 cfg_param_022; 369 __u32 cfg_param_023; 370 __u32 cfg_param_024; 371 __u32 cfg_param_025; 372 __u32 cfg_param_026; 373 __u32 cfg_param_027; 374 __u32 cfg_param_028; 375 __u32 cfg_param_029; 376 __u32 cfg_param_030; 377 __u32 cfg_param_031; 378 __u32 cfg_param_032; 379 __u32 cfg_param_033; 380 __u32 cfg_param_034; 381 __u32 cfg_param_035; 382 __u32 cfg_param_036; 383 __u32 cfg_param_037; 384 __u32 cfg_param_038; 385 __u32 cfg_param_039; 386 __u32 cfg_param_040; 387 __u32 cfg_param_041; 388 __u32 cfg_param_042; 389 __u32 cfg_param_043; 390 __u32 cfg_param_044; 391 __u32 cfg_param_045; 392 __u32 cfg_param_046; 393 __u32 cfg_param_047; 394 __u32 cfg_param_048; 395 __u32 cfg_param_049; 396 __u32 cfg_param_050; 397 __u32 cfg_param_051; 398 __u32 cfg_param_052; 399 __u32 cfg_param_053; 400 }; 401 402 #define DITHER_MATRIX_SZ 16 403 404 /** 405 * struct drm_msm_dither - dither feature structure 406 * @flags: for customizing operations 407 * @temporal_en: temperal dither enable 408 * @c0_bitdepth: c0 component bit depth 409 * @c1_bitdepth: c1 component bit depth 410 * @c2_bitdepth: c2 component bit depth 411 * @c3_bitdepth: c2 component bit depth 412 * @matrix: dither strength matrix 413 */ 414 struct drm_msm_dither { 415 __u64 flags; 416 __u32 temporal_en; 417 __u32 c0_bitdepth; 418 __u32 c1_bitdepth; 419 __u32 c2_bitdepth; 420 __u32 c3_bitdepth; 421 __u32 matrix[DITHER_MATRIX_SZ]; 422 }; 423 424 /** 425 * struct drm_msm_pa_dither - dspp dither feature structure 426 * @flags: for customizing operations 427 * @strength: dither strength 428 * @offset_en: offset enable bit 429 * @matrix: dither data matrix 430 */ 431 #define DRM_MSM_PA_DITHER 432 struct drm_msm_pa_dither { 433 __u64 flags; 434 __u32 strength; 435 __u32 offset_en; 436 __u32 matrix[DITHER_MATRIX_SZ]; 437 }; 438 439 #endif /* _MSM_DRM_PP_H_ */ 440
