1 /** @file 2 * 3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2016, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef _LPC_LIB_H_ 17 #define _LPC_LIB_H_ 18 19 #include <Uefi.h> 20 21 #define PCIE_SUBSYS_IO_MUX 0xA0170000 22 #define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) 23 #define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) 24 #define PCIE_SUBSYS_IOMG036 (PCIE_SUBSYS_IO_MUX + 0x90) 25 #define PCIE_SUBSYS_IOMG045 (PCIE_SUBSYS_IO_MUX + 0xB4) 26 #define PCIE_SUBSYS_IOMG046 (PCIE_SUBSYS_IO_MUX + 0xB8) 27 #define PCIE_SUBSYS_IOMG047 (PCIE_SUBSYS_IO_MUX + 0xBC) 28 #define PCIE_SUBSYS_IOMG048 (PCIE_SUBSYS_IO_MUX + 0xC0) 29 #define PCIE_SUBSYS_IOMG049 (PCIE_SUBSYS_IO_MUX + 0xC4) 30 #define PCIE_SUBSYS_IOMG050 (PCIE_SUBSYS_IO_MUX + 0xC8) 31 32 #define IO_WRAP_CTRL_BASE 0xA0100000 33 #define SC_LPC_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a0) 34 #define SC_LPC_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03a4) 35 #define SC_LPC_BUS_CLK_EN_REG (IO_WRAP_CTRL_BASE + 0x03a8) 36 #define SC_LPC_BUS_CLK_DIS_REG (IO_WRAP_CTRL_BASE + 0x03ac) 37 #define SC_LPC_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ad8) 38 #define SC_LPC_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0adc) 39 #define SC_LPC_BUS_RESET_REQ (IO_WRAP_CTRL_BASE + 0x0ae0) 40 #define SC_LPC_BUS_RESET_DREQ (IO_WRAP_CTRL_BASE + 0x0ae4) 41 #define SC_LPC_CTRL_REG (IO_WRAP_CTRL_BASE + 0x2028) 42 43 44 #define LPC_BASE 0xA01B0000 45 #define LPC_START_REG (LPC_BASE + 0x00) 46 #define LPC_OP_STATUS_REG (LPC_BASE + 0x04) 47 #define LPC_IRQ_ST_REG (LPC_BASE + 0x08) 48 #define LPC_OP_LEN_REG (LPC_BASE + 0x10) 49 #define LPC_CMD_REG (LPC_BASE + 0x14) 50 #define LPC_FWH_ID_MSIZE_REG (LPC_BASE + 0x18) 51 #define LPC_ADDR_REG (LPC_BASE + 0x20) 52 #define LPC_WDATA_REG (LPC_BASE + 0x24) 53 #define LPC_RDATA_REG (LPC_BASE + 0x28) 54 #define LPC_LONG_CNT_REG (LPC_BASE + 0x30) 55 #define LPC_TX_FIFO_ST_REG (LPC_BASE + 0x50) 56 #define LPC_RX_FIFO_ST_REG (LPC_BASE + 0x54) 57 #define LPC_TIME_OUT_REG (LPC_BASE + 0x58) 58 #define LPC_SIRQ_CTRL0_REG (LPC_BASE + 0x80) 59 #define LPC_SIRQ_CTRL1_REG (LPC_BASE + 0x84) 60 #define LPC_SIRQ_INT_REG (LPC_BASE + 0x90) 61 #define LPC_SIRQ_INT_MASK_REG (LPC_BASE + 0x94) 62 #define LPC_SIRQ_STAT_REG (LPC_BASE + 0xA0) 63 64 #define LPC_FIFO_LEN (16) 65 66 typedef enum{ 67 LPC_ADDR_MODE_INCREASE, 68 LPC_ADDR_MODE_SINGLE 69 }LPC_ADDR_MODE; 70 71 typedef enum{ 72 LPC_TYPE_IO, 73 LPC_TYPE_MEM, 74 LPC_TYPE_FWH 75 }LPC_TYPE; 76 77 78 typedef union { 79 struct{ 80 UINT32 lpc_wr:1; 81 UINT32 lpc_type:2; 82 UINT32 same_addr:1; 83 UINT32 resv:28; 84 }bits; 85 UINT32 u32; 86 }LPC_CMD_STRUCT; 87 88 typedef union { 89 struct{ 90 UINT32 op_len:5; 91 UINT32 resv:27; 92 }bits; 93 UINT32 u32; 94 }LPC_OP_LEN_STRUCT; 95 96 97 VOID LpcInit(VOID); 98 BOOLEAN LpcIdle(VOID); 99 EFI_STATUS LpcByteWrite( 100 IN UINT32 Addr, 101 IN UINT8 Data); 102 EFI_STATUS LpcByteRead( 103 IN UINT32 Addr, 104 IN OUT UINT8 *Data); 105 106 EFI_STATUS LpcWrite( 107 IN UINT32 Addr, 108 IN UINT8 *Data, 109 IN UINT8 Len); 110 111 #endif 112 113 114
