1 /** @file 2 * 3 * Copyright (c) 2015, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2015, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef _PLATFORM_SYS_CTRL_LIB_H_ 17 #define _PLATFORM_SYS_CTRL_LIB_H_ 18 19 #define PACKAGE_16CORE 0 20 #define PACKAGE_32CORE 1 21 #define PACKAGE_RESERVED 2 22 #define PACKAGE_TYPE_NUM 3 23 24 UINT32 PlatformGetPackageType (VOID); 25 26 VOID DisplayCpuInfo (VOID); 27 UINT32 CheckChipIsEc(VOID); 28 29 UINTN PlatformGetPll (UINT32 NodeId, UINTN Pll); 30 31 #define DJTAG_READ_INVALID_VALUE 0xFFFFFFFF 32 #define DJTAG_CHAIN_ID_AA 1 33 #define DJTAG_CHAIN_ID_LLC 4 34 35 36 #define SC_DJTAG_MSTR_EN_OFFSET 0x6800 37 #define SC_DJTAG_MSTR_START_EN_OFFSET 0x6804 38 #define SC_DJTAG_SEC_ACC_EN_OFFSET 0x6808 39 #define SC_DJTAG_DEBUG_MODULE_SEL_OFFSET 0x680C 40 #define SC_DJTAG_MSTR_WR_OFFSET 0x6810 41 #define SC_DJTAG_CHAIN_UNIT_CFG_EN_OFFSET 0x6814 42 #define SC_DJTAG_MSTR_ADDR_OFFSET 0x6818 43 #define SC_DJTAG_MSTR_DATA_OFFSET 0x681C 44 #define SC_DJTAG_TMOUT_OFFSET 0x6820 45 #define SC_TDRE_OP_ADDR_OFFSET 0x6824 46 #define SC_TDRE_WDATA_OFFSET 0x6828 47 #define SC_TDRE_REPAIR_EN_OFFSET 0x682C 48 #define SC_DJTAG_RD_DATA0_OFFSET 0xE800 49 #define SC_TDRE_RDATA0_OFFSET 0xE830 50 51 52 UINTN PlatformGetI2cBase(UINT32 Socket,UINT8 Port); 53 54 VOID PlatformAddressMapCleanUp (VOID); 55 VOID PlatformDisableDdrWindow (VOID); 56 57 VOID PlatformEnableArchTimer (VOID); 58 59 EFI_STATUS 60 DawFindFreeWindow (UINTN Socket, UINTN *DawIndex); 61 62 VOID DawSetWindow (UINTN Socket, UINTN WindowIndex, UINT32 Value); 63 64 VOID DJTAG_TDRE_WRITE(UINT32 Offset, UINT32 Value, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair); 65 66 UINT32 DJTAG_TDRE_READ(UINT32 Offset, UINT32 ChainID, UINT32 NodeId, BOOLEAN Repair); 67 68 VOID RemoveRoceReset(VOID); 69 70 UINTN PlatformGetDdrChannel (VOID); 71 72 VOID ITSCONFIG (VOID); 73 74 VOID MN_CONFIG (VOID); 75 76 VOID SmmuConfigForOS (VOID); 77 VOID SmmuConfigForBios (VOID); 78 79 VOID StartupAp (VOID); 80 81 VOID LlcCleanInvalidate (VOID); 82 83 UINTN PlatformGetCpuFreq (UINT8 Socket); 84 VOID ClearInterruptStatus(VOID); 85 86 UINTN PlatformGetCoreCount (VOID); 87 VOID DAWConfigEn(UINT32 socket); 88 89 VOID DResetUsb (); 90 UINT32 PlatformGetEhciBase (); 91 UINT32 PlatformGetOhciBase (); 92 VOID PlatformPllInit(); 93 // PLL initialization for super IO clusters. 94 VOID SiclPllInit(UINT32 SclId); 95 VOID PlatformDeviceDReset(); 96 VOID PlatformGicdInit(); 97 VOID PlatformLpcInit(); 98 // Synchronize architecture timer counter between different super computing 99 // clusters. 100 VOID PlatformArchTimerSynchronize(VOID); 101 VOID PlatformEventBroadcastConfig(VOID); 102 UINTN GetDjtagRegBase(UINT32 NodeId); 103 VOID LlcCleanInvalidateAsm(VOID); 104 VOID PlatformMdioInit(VOID); 105 106 #endif 107
