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      1 COMPHY configuration
      2 ---------------------------
      3 In order to configure ComPhy library, following PCDs are available:
      4 
      5   gMarvellTokenSpaceGuid.PcdComPhyChipCount
      6 
      7 Indicates how many different chips are placed on board. So far, up to 4 chips
      8 are supported.
      9 
     10 Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
     11 important, but configuration will be set for first PcdComPhyChipCount chips).
     12 
     13 Every chip has 8 ComPhy PCDs and three of them concern lanes settings for this
     14 chip. Below is example for the first chip (Chip0).
     15 
     16 General PCDs:
     17 
     18   gMarvellTokenSpaceGuid.PcdChip0Compatible
     19 
     20 Unicode string indicating type of chip - currently supported is
     21 { L"Cp110" }
     22 
     23   gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress
     24 
     25 Indicates COMPHY unit base address.
     26 
     27   gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress
     28 
     29 Indicates Hpipe3 unit base address.
     30 
     31   gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount
     32 
     33 Indicates number of bits that are allocated for every MUX in the
     34 COMPHY-selector register.
     35 
     36   gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes
     37 
     38 Indicates maximum ComPhy lanes number.
     39 
     40 Next three PCDs are in unicode string format containing settings for up to 10
     41 lanes. Setting for each one is separated with semicolon. These PCDs form
     42 structure describing outputs of PHY integrated in simple cihp.
     43 Below is example for the first chip (Chip0).
     44 
     45   gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
     46 
     47 Unicode string indicating PHY types. Currently supported are:
     48 
     49 { L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3",
     50 L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0",
     51 L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII",
     52 L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE",
     53 L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0",
     54 L"RXAUI1", L"KR" }
     55 
     56 Below documents describes some of above interfaces' types:
     57 
     58 SGMII, QSGMII, XAUI - IEEE 802.3
     59 KR - IEEE 802.3a
     60 RXAUI - RXAUI Interface and RXAUI Adapter Specification, Marvell
     61 
     62   gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
     63 
     64 Indicates PHY speeds in MHz. Currently supported are:
     65 
     66 { 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 10310 }
     67 
     68   gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
     69 
     70 Indicates lane polarity invert.
     71 
     72 Example
     73 -------
     74   #ComPhy
     75   gMarvellTokenSpaceGuid.PcdComPhyChipCount|1
     76 
     77   gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6
     78   gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000
     79   gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000
     80   gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4
     81   gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110"
     82 
     83   gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2"
     84   gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;1250;5000;5000;5000"
     85 
     86