1 Pp2Dxe porting guide 2 -------------------- 3 Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs 4 are required to operate: 5 6 Number of ports/network interfaces: 7 gMarvellTokenSpaceGuid.PcdPp2NumPorts 8 9 Addresses of PHY devices: 10 gMarvellTokenSpaceGuid.PcdPhySmiAddresses 11 12 Identificators of PP2 ports: 13 gMarvellTokenSpaceGuid.PcdPp2PortIds 14 15 Indexes used in GOP operation: 16 gMarvellTokenSpaceGuid.PcdPp2GopIndexes 17 18 Set to 0x1 for always-up interface, 0x0 otherwise: 19 gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp 20 21 Values corresponding to PHY_SPEED enum: 22 gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed 23 24 PHY_SPEED (in Mbps) is defined as follows: 25 typedef enum { 26 0 NO_SPEED, 27 1 SPEED_10, 28 2 SPEED_100, 29 3 SPEED_1000, 30 4 SPEED_2500, 31 5 SPEED_10000 32 } PHY_SPEED; 33 34 Base address of shared register space of PP2: 35 gMarvellTokenSpaceGuid.PcdPp2SharedAddress 36 37 Spacing between consecutive GMAC register spaces: 38 gMarvellTokenSpaceGuid.PcdPp2GmacDevSize 39 40 Base address of GMAC: 41 gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress 42 43 Spacing between consecutive XLG register spaces: 44 gMarvellTokenSpaceGuid.PcdPp2XlgDevSize 45 46 Base address of XLG: 47 gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress 48 49 Base address of RFU1: 50 gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress 51 52 Base address of SMI: 53 gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress 54 55 TCLK frequency in Hz: 56 gMarvellTokenSpaceGuid.PcdPp2ClockFrequency 57 58 GMAC and XLG addresses are computed as follows: 59 address = base_address + dev_size * gop_index 60
