1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /dts-v1/; 32 33 /memreserve/ 0x80000000 0x00010000; 34 35 / { 36 }; 37 38 / { 39 model = "FVP Base"; 40 compatible = "arm,vfp-base", "arm,vexpress"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 chosen { 46 stdout-path = "serial0"; 47 }; 48 49 aliases { 50 serial0 = &v2m_serial0; 51 serial1 = &v2m_serial1; 52 serial2 = &v2m_serial2; 53 serial3 = &v2m_serial3; 54 }; 55 56 psci { 57 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 58 method = "smc"; 59 cpu_suspend = <0xc4000001>; 60 cpu_off = <0x84000002>; 61 cpu_on = <0xc4000003>; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 }; 83 84 cluster1 { 85 core0 { 86 cpu = <&CPU4>; 87 }; 88 core1 { 89 cpu = <&CPU5>; 90 }; 91 core2 { 92 cpu = <&CPU6>; 93 }; 94 core3 { 95 cpu = <&CPU7>; 96 }; 97 }; 98 }; 99 100 idle-states { 101 entry-method = "arm,psci"; 102 103 CPU_SLEEP_0: cpu-sleep-0 { 104 compatible = "arm,idle-state"; 105 local-timer-stop; 106 arm,psci-suspend-param = <0x0010000>; 107 entry-latency-us = <40>; 108 exit-latency-us = <100>; 109 min-residency-us = <150>; 110 }; 111 112 CLUSTER_SLEEP_0: cluster-sleep-0 { 113 compatible = "arm,idle-state"; 114 local-timer-stop; 115 arm,psci-suspend-param = <0x1010000>; 116 entry-latency-us = <500>; 117 exit-latency-us = <1000>; 118 min-residency-us = <2500>; 119 }; 120 }; 121 122 CPU0:cpu@0 { 123 device_type = "cpu"; 124 compatible = "arm,armv8"; 125 reg = <0x0 0x0>; 126 enable-method = "psci"; 127 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 128 }; 129 130 CPU1:cpu@1 { 131 device_type = "cpu"; 132 compatible = "arm,armv8"; 133 reg = <0x0 0x1>; 134 enable-method = "psci"; 135 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 136 }; 137 138 CPU2:cpu@2 { 139 device_type = "cpu"; 140 compatible = "arm,armv8"; 141 reg = <0x0 0x2>; 142 enable-method = "psci"; 143 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 144 }; 145 146 CPU3:cpu@3 { 147 device_type = "cpu"; 148 compatible = "arm,armv8"; 149 reg = <0x0 0x3>; 150 enable-method = "psci"; 151 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 152 }; 153 154 CPU4:cpu@100 { 155 device_type = "cpu"; 156 compatible = "arm,armv8"; 157 reg = <0x0 0x100>; 158 enable-method = "psci"; 159 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 160 }; 161 162 CPU5:cpu@101 { 163 device_type = "cpu"; 164 compatible = "arm,armv8"; 165 reg = <0x0 0x101>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 168 }; 169 170 CPU6:cpu@102 { 171 device_type = "cpu"; 172 compatible = "arm,armv8"; 173 reg = <0x0 0x102>; 174 enable-method = "psci"; 175 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 176 }; 177 178 CPU7:cpu@103 { 179 device_type = "cpu"; 180 compatible = "arm,armv8"; 181 reg = <0x0 0x103>; 182 enable-method = "psci"; 183 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 184 }; 185 }; 186 187 memory@80000000 { 188 device_type = "memory"; 189 reg = <0x00000000 0x80000000 0 0x7F000000>, 190 <0x00000008 0x80000000 0 0x80000000>; 191 }; 192 193 gic: interrupt-controller@2f000000 { 194 compatible = "arm,gic-v3"; 195 #interrupt-cells = <3>; 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges; 199 interrupt-controller; 200 reg = <0x0 0x2f000000 0 0x10000>, // GICD 201 <0x0 0x2f100000 0 0x200000>, // GICR 202 <0x0 0x2c000000 0 0x2000>, // GICC 203 <0x0 0x2c010000 0 0x2000>, // GICH 204 <0x0 0x2c02f000 0 0x2000>; // GICV 205 interrupts = <1 9 4>; 206 207 its: its@2f020000 { 208 compatible = "arm,gic-v3-its"; 209 msi-controller; 210 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS 211 }; 212 }; 213 214 timer { 215 compatible = "arm,armv8-timer"; 216 interrupts = <1 13 0xff01>, 217 <1 14 0xff01>, 218 <1 11 0xff01>, 219 <1 10 0xff01>; 220 clock-frequency = <100000000>; 221 }; 222 223 timer@2a810000 { 224 compatible = "arm,armv7-timer-mem"; 225 reg = <0x0 0x2a810000 0x0 0x10000>; 226 clock-frequency = <100000000>; 227 #address-cells = <2>; 228 #size-cells = <2>; 229 ranges; 230 frame@2a830000 { 231 frame-number = <1>; 232 interrupts = <0 26 4>; 233 reg = <0x0 0x2a830000 0x0 0x10000>; 234 }; 235 }; 236 237 pmu { 238 compatible = "arm,armv8-pmuv3"; 239 interrupts = <0 60 4>, 240 <0 61 4>, 241 <0 62 4>, 242 <0 63 4>; 243 }; 244 245 smb { 246 compatible = "simple-bus"; 247 248 #address-cells = <2>; 249 #size-cells = <1>; 250 ranges = <0 0 0 0x08000000 0x04000000>, 251 <1 0 0 0x14000000 0x04000000>, 252 <2 0 0 0x18000000 0x04000000>, 253 <3 0 0 0x1c000000 0x04000000>, 254 <4 0 0 0x0c000000 0x04000000>, 255 <5 0 0 0x10000000 0x04000000>; 256 257 #interrupt-cells = <1>; 258 interrupt-map-mask = <0 0 63>; 259 interrupt-map = <0 0 0 &gic 0 0 0 0 4>, 260 <0 0 1 &gic 0 0 0 1 4>, 261 <0 0 2 &gic 0 0 0 2 4>, 262 <0 0 3 &gic 0 0 0 3 4>, 263 <0 0 4 &gic 0 0 0 4 4>, 264 <0 0 5 &gic 0 0 0 5 4>, 265 <0 0 6 &gic 0 0 0 6 4>, 266 <0 0 7 &gic 0 0 0 7 4>, 267 <0 0 8 &gic 0 0 0 8 4>, 268 <0 0 9 &gic 0 0 0 9 4>, 269 <0 0 10 &gic 0 0 0 10 4>, 270 <0 0 11 &gic 0 0 0 11 4>, 271 <0 0 12 &gic 0 0 0 12 4>, 272 <0 0 13 &gic 0 0 0 13 4>, 273 <0 0 14 &gic 0 0 0 14 4>, 274 <0 0 15 &gic 0 0 0 15 4>, 275 <0 0 16 &gic 0 0 0 16 4>, 276 <0 0 17 &gic 0 0 0 17 4>, 277 <0 0 18 &gic 0 0 0 18 4>, 278 <0 0 19 &gic 0 0 0 19 4>, 279 <0 0 20 &gic 0 0 0 20 4>, 280 <0 0 21 &gic 0 0 0 21 4>, 281 <0 0 22 &gic 0 0 0 22 4>, 282 <0 0 23 &gic 0 0 0 23 4>, 283 <0 0 24 &gic 0 0 0 24 4>, 284 <0 0 25 &gic 0 0 0 25 4>, 285 <0 0 26 &gic 0 0 0 26 4>, 286 <0 0 27 &gic 0 0 0 27 4>, 287 <0 0 28 &gic 0 0 0 28 4>, 288 <0 0 29 &gic 0 0 0 29 4>, 289 <0 0 30 &gic 0 0 0 30 4>, 290 <0 0 31 &gic 0 0 0 31 4>, 291 <0 0 32 &gic 0 0 0 32 4>, 292 <0 0 33 &gic 0 0 0 33 4>, 293 <0 0 34 &gic 0 0 0 34 4>, 294 <0 0 35 &gic 0 0 0 35 4>, 295 <0 0 36 &gic 0 0 0 36 4>, 296 <0 0 37 &gic 0 0 0 37 4>, 297 <0 0 38 &gic 0 0 0 38 4>, 298 <0 0 39 &gic 0 0 0 39 4>, 299 <0 0 40 &gic 0 0 0 40 4>, 300 <0 0 41 &gic 0 0 0 41 4>, 301 <0 0 42 &gic 0 0 0 42 4>; 302 303 /include/ "rtsm_ve-motherboard-no_psci.dtsi" 304 }; 305 306 panels { 307 panel@0 { 308 compatible = "panel"; 309 mode = "XVGA"; 310 refresh = <60>; 311 xres = <1024>; 312 yres = <768>; 313 pixclock = <15748>; 314 left_margin = <152>; 315 right_margin = <48>; 316 upper_margin = <23>; 317 lower_margin = <3>; 318 hsync_len = <104>; 319 vsync_len = <4>; 320 sync = <0>; 321 vmode = "FB_VMODE_NONINTERLACED"; 322 tim2 = "TIM2_BCD", "TIM2_IPC"; 323 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; 324 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; 325 bpp = <16>; 326 }; 327 }; 328 }; 329
