1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of the ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /dts-v1/; 32 33 /memreserve/ 0x80000000 0x00010000; 34 35 / { 36 }; 37 38 / { 39 model = "FVP Foundation"; 40 compatible = "arm,fvp-base", "arm,vexpress"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 chosen { 46 stdout-path = "serial0"; 47 }; 48 49 aliases { 50 serial0 = &v2m_serial0; 51 serial1 = &v2m_serial1; 52 serial2 = &v2m_serial2; 53 serial3 = &v2m_serial3; 54 }; 55 56 psci { 57 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 58 method = "smc"; 59 cpu_suspend = <0xc4000001>; 60 cpu_off = <0x84000002>; 61 cpu_on = <0xc4000003>; 62 sys_poweroff = <0x84000008>; 63 sys_reset = <0x84000009>; 64 }; 65 66 cpus { 67 #address-cells = <2>; 68 #size-cells = <0>; 69 70 cpu-map { 71 cluster0 { 72 core0 { 73 cpu = <&CPU0>; 74 }; 75 core1 { 76 cpu = <&CPU1>; 77 }; 78 core2 { 79 cpu = <&CPU2>; 80 }; 81 core3 { 82 cpu = <&CPU3>; 83 }; 84 }; 85 }; 86 87 idle-states { 88 entry-method = "arm,psci"; 89 90 CPU_SLEEP_0: cpu-sleep-0 { 91 compatible = "arm,idle-state"; 92 local-timer-stop; 93 arm,psci-suspend-param = <0x0010000>; 94 entry-latency-us = <40>; 95 exit-latency-us = <100>; 96 min-residency-us = <150>; 97 }; 98 99 CLUSTER_SLEEP_0: cluster-sleep-0 { 100 compatible = "arm,idle-state"; 101 local-timer-stop; 102 arm,psci-suspend-param = <0x1010000>; 103 entry-latency-us = <500>; 104 exit-latency-us = <1000>; 105 min-residency-us = <2500>; 106 }; 107 }; 108 109 CPU0:cpu@0 { 110 device_type = "cpu"; 111 compatible = "arm,armv8"; 112 reg = <0x0 0x0>; 113 enable-method = "psci"; 114 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 115 }; 116 117 CPU1:cpu@1 { 118 device_type = "cpu"; 119 compatible = "arm,armv8"; 120 reg = <0x0 0x1>; 121 enable-method = "psci"; 122 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 123 }; 124 125 CPU2:cpu@2 { 126 device_type = "cpu"; 127 compatible = "arm,armv8"; 128 reg = <0x0 0x2>; 129 enable-method = "psci"; 130 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 131 }; 132 133 CPU3:cpu@3 { 134 device_type = "cpu"; 135 compatible = "arm,armv8"; 136 reg = <0x0 0x3>; 137 enable-method = "psci"; 138 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 139 }; 140 }; 141 142 memory@80000000 { 143 device_type = "memory"; 144 reg = <0x00000000 0x80000000 0 0x7F000000>, 145 <0x00000008 0x80000000 0 0x80000000>; 146 }; 147 148 gic: interrupt-controller@2f000000 { 149 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 150 #interrupt-cells = <3>; 151 #address-cells = <0>; 152 interrupt-controller; 153 reg = <0x0 0x2f000000 0 0x10000>, 154 <0x0 0x2c000000 0 0x2000>, 155 <0x0 0x2c010000 0 0x2000>, 156 <0x0 0x2c02F000 0 0x2000>; 157 interrupts = <1 9 0xf04>; 158 }; 159 160 timer { 161 compatible = "arm,armv8-timer"; 162 interrupts = <1 13 0xff01>, 163 <1 14 0xff01>, 164 <1 11 0xff01>, 165 <1 10 0xff01>; 166 clock-frequency = <100000000>; 167 }; 168 169 timer@2a810000 { 170 compatible = "arm,armv7-timer-mem"; 171 reg = <0x0 0x2a810000 0x0 0x10000>; 172 clock-frequency = <100000000>; 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges; 176 frame@2a830000 { 177 frame-number = <1>; 178 interrupts = <0 26 4>; 179 reg = <0x0 0x2a830000 0x0 0x10000>; 180 }; 181 }; 182 183 pmu { 184 compatible = "arm,armv8-pmuv3"; 185 interrupts = <0 60 4>, 186 <0 61 4>, 187 <0 62 4>, 188 <0 63 4>; 189 }; 190 191 smb { 192 compatible = "simple-bus"; 193 194 #address-cells = <2>; 195 #size-cells = <1>; 196 ranges = <0 0 0 0x08000000 0x04000000>, 197 <1 0 0 0x14000000 0x04000000>, 198 <2 0 0 0x18000000 0x04000000>, 199 <3 0 0 0x1c000000 0x04000000>, 200 <4 0 0 0x0c000000 0x04000000>, 201 <5 0 0 0x10000000 0x04000000>; 202 203 #interrupt-cells = <1>; 204 interrupt-map-mask = <0 0 63>; 205 interrupt-map = <0 0 0 &gic 0 0 4>, 206 <0 0 1 &gic 0 1 4>, 207 <0 0 2 &gic 0 2 4>, 208 <0 0 3 &gic 0 3 4>, 209 <0 0 4 &gic 0 4 4>, 210 <0 0 5 &gic 0 5 4>, 211 <0 0 6 &gic 0 6 4>, 212 <0 0 7 &gic 0 7 4>, 213 <0 0 8 &gic 0 8 4>, 214 <0 0 9 &gic 0 9 4>, 215 <0 0 10 &gic 0 10 4>, 216 <0 0 11 &gic 0 11 4>, 217 <0 0 12 &gic 0 12 4>, 218 <0 0 13 &gic 0 13 4>, 219 <0 0 14 &gic 0 14 4>, 220 <0 0 15 &gic 0 15 4>, 221 <0 0 16 &gic 0 16 4>, 222 <0 0 17 &gic 0 17 4>, 223 <0 0 18 &gic 0 18 4>, 224 <0 0 19 &gic 0 19 4>, 225 <0 0 20 &gic 0 20 4>, 226 <0 0 21 &gic 0 21 4>, 227 <0 0 22 &gic 0 22 4>, 228 <0 0 23 &gic 0 23 4>, 229 <0 0 24 &gic 0 24 4>, 230 <0 0 25 &gic 0 25 4>, 231 <0 0 26 &gic 0 26 4>, 232 <0 0 27 &gic 0 27 4>, 233 <0 0 28 &gic 0 28 4>, 234 <0 0 29 &gic 0 29 4>, 235 <0 0 30 &gic 0 30 4>, 236 <0 0 31 &gic 0 31 4>, 237 <0 0 32 &gic 0 32 4>, 238 <0 0 33 &gic 0 33 4>, 239 <0 0 34 &gic 0 34 4>, 240 <0 0 35 &gic 0 35 4>, 241 <0 0 36 &gic 0 36 4>, 242 <0 0 37 &gic 0 37 4>, 243 <0 0 38 &gic 0 38 4>, 244 <0 0 39 &gic 0 39 4>, 245 <0 0 40 &gic 0 40 4>, 246 <0 0 41 &gic 0 41 4>, 247 <0 0 42 &gic 0 42 4>; 248 249 /include/ "fvp-foundation-motherboard.dtsi" 250 }; 251 }; 252
