1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 10 OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 11 ENTRY(bl1_entrypoint) 12 13 MEMORY { 14 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 15 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 16 } 17 18 SECTIONS 19 { 20 . = BL1_RO_BASE; 21 ASSERT(. == ALIGN(4096), 22 "BL1_RO_BASE address is not aligned on a page boundary.") 23 24 #if SEPARATE_CODE_AND_RODATA 25 .text . : { 26 __TEXT_START__ = .; 27 *bl1_entrypoint.o(.text*) 28 *(.text*) 29 *(.vectors) 30 . = NEXT(4096); 31 __TEXT_END__ = .; 32 } >ROM 33 34 .rodata . : { 35 __RODATA_START__ = .; 36 *(.rodata*) 37 38 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 39 . = ALIGN(8); 40 __PARSER_LIB_DESCS_START__ = .; 41 KEEP(*(.img_parser_lib_descs)) 42 __PARSER_LIB_DESCS_END__ = .; 43 44 /* 45 * Ensure 8-byte alignment for cpu_ops so that its fields are also 46 * aligned. Also ensure cpu_ops inclusion. 47 */ 48 . = ALIGN(8); 49 __CPU_OPS_START__ = .; 50 KEEP(*(cpu_ops)) 51 __CPU_OPS_END__ = .; 52 53 /* 54 * No need to pad out the .rodata section to a page boundary. Next is 55 * the .data section, which can mapped in ROM with the same memory 56 * attributes as the .rodata section. 57 */ 58 __RODATA_END__ = .; 59 } >ROM 60 #else 61 ro . : { 62 __RO_START__ = .; 63 *bl1_entrypoint.o(.text*) 64 *(.text*) 65 *(.rodata*) 66 67 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 68 . = ALIGN(8); 69 __PARSER_LIB_DESCS_START__ = .; 70 KEEP(*(.img_parser_lib_descs)) 71 __PARSER_LIB_DESCS_END__ = .; 72 73 /* 74 * Ensure 8-byte alignment for cpu_ops so that its fields are also 75 * aligned. Also ensure cpu_ops inclusion. 76 */ 77 . = ALIGN(8); 78 __CPU_OPS_START__ = .; 79 KEEP(*(cpu_ops)) 80 __CPU_OPS_END__ = .; 81 82 *(.vectors) 83 __RO_END__ = .; 84 } >ROM 85 #endif 86 87 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 88 "cpu_ops not defined for this platform.") 89 90 . = BL1_RW_BASE; 91 ASSERT(BL1_RW_BASE == ALIGN(4096), 92 "BL1_RW_BASE address is not aligned on a page boundary.") 93 94 /* 95 * The .data section gets copied from ROM to RAM at runtime. 96 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes 97 * aligned regions in it. 98 * Its VMA must be page-aligned as it marks the first read/write page. 99 * 100 * It must be placed at a lower address than the stacks if the stack 101 * protector is enabled. Alternatively, the .data.stack_protector_canary 102 * section can be placed independently of the main .data section. 103 */ 104 .data . : ALIGN(16) { 105 __DATA_RAM_START__ = .; 106 *(.data*) 107 __DATA_RAM_END__ = .; 108 } >RAM AT>ROM 109 110 stacks . (NOLOAD) : { 111 __STACKS_START__ = .; 112 *(tzfw_normal_stacks) 113 __STACKS_END__ = .; 114 } >RAM 115 116 /* 117 * The .bss section gets initialised to 0 at runtime. 118 * Its base address should be 16-byte aligned for better performance of the 119 * zero-initialization code. 120 */ 121 .bss : ALIGN(16) { 122 __BSS_START__ = .; 123 *(.bss*) 124 *(COMMON) 125 __BSS_END__ = .; 126 } >RAM 127 128 /* 129 * The xlat_table section is for full, aligned page tables (4K). 130 * Removing them from .bss avoids forcing 4K alignment on 131 * the .bss section and eliminates the unecessary zero init 132 */ 133 xlat_table (NOLOAD) : { 134 *(xlat_table) 135 } >RAM 136 137 #if USE_COHERENT_MEM 138 /* 139 * The base address of the coherent memory section must be page-aligned (4K) 140 * to guarantee that the coherent data are stored on their own pages and 141 * are not mixed with normal data. This is required to set up the correct 142 * memory attributes for the coherent data page tables. 143 */ 144 coherent_ram (NOLOAD) : ALIGN(4096) { 145 __COHERENT_RAM_START__ = .; 146 *(tzfw_coherent_mem) 147 __COHERENT_RAM_END_UNALIGNED__ = .; 148 /* 149 * Memory page(s) mapped to this section will be marked 150 * as device memory. No other unexpected data must creep in. 151 * Ensure the rest of the current memory page is unused. 152 */ 153 . = NEXT(4096); 154 __COHERENT_RAM_END__ = .; 155 } >RAM 156 #endif 157 158 __BL1_RAM_START__ = ADDR(.data); 159 __BL1_RAM_END__ = .; 160 161 __DATA_ROM_START__ = LOADADDR(.data); 162 __DATA_SIZE__ = SIZEOF(.data); 163 164 /* 165 * The .data section is the last PROGBITS section so its end marks the end 166 * of BL1's actual content in Trusted ROM. 167 */ 168 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 169 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 170 "BL1's ROM content has exceeded its limit.") 171 172 __BSS_SIZE__ = SIZEOF(.bss); 173 174 #if USE_COHERENT_MEM 175 __COHERENT_RAM_UNALIGNED_SIZE__ = 176 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 177 #endif 178 179 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 180 } 181
