1 Tegra SoCs - Overview 2 ===================== 3 4 - .. rubric:: T210 5 :name: t210 6 7 T210 has Quad ARM Cortex-A57 cores in a switched configuration with a 8 companion set of quad ARM Cortex-A53 cores. The Cortex-A57 and A53 cores 9 support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code 10 including legacy ARMv7 applications. The Cortex-A57 processors each have 11 48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared 12 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction 13 and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache. 14 15 - .. rubric:: T132 16 :name: t132 17 18 Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is 19 fully ARMv8 architecture compatible. Each of the two Denver cores 20 implements a 7-way superscalar microarchitecture (up to 7 concurrent 21 micro-ops can be executed per clock), and includes a 128KB 4-way L1 22 instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2 23 cache, which services both cores. 24 25 Denver implements an innovative process called Dynamic Code Optimization, 26 which optimizes frequently used software routines at runtime into dense, 27 highly tuned microcode-equivalent routines. These are stored in a 28 dedicated, 128MB main-memory-based optimization cache. After being read 29 into the instruction cache, the optimized micro-ops are executed, 30 re-fetched and executed from the instruction cache as long as needed and 31 capacity allows. 32 33 Effectively, this reduces the need to re-optimize the software routines. 34 Instead of using hardware to extract the instruction-level parallelism 35 (ILP) inherent in the code, Denver extracts the ILP once via software 36 techniques, and then executes those routines repeatedly, thus amortizing 37 the cost of ILP extraction over the many execution instances. 38 39 Denver also features new low latency power-state transitions, in addition 40 to extensive power-gating and dynamic voltage and clock scaling based on 41 workloads. 42 43 Directory structure 44 =================== 45 46 - plat/nvidia/tegra/common - Common code for all Tegra SoCs 47 - plat/nvidia/tegra/soc/txxx - Chip specific code 48 49 Trusted OS dispatcher 50 ===================== 51 52 Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of 53 them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd' 54 on the command line while preparing a bl31 image. This allows other Trusted OS 55 vendors to use the upstream code and include their dispatchers in the image 56 without changing any makefiles. 57 58 Preparing the BL31 image to run on Tegra SoCs 59 ============================================= 60 61 .. code:: shell 62 63 CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ 64 TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31 65 66 Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>`` 67 to the build command line. 68 69 The Tegra platform code expects a pointer to the following platform specific 70 structure via 'x1' register from the BL2 layer which is used by the 71 bl31\_early\_platform\_setup() handler to extract the TZDRAM carveout base and 72 size for loading the Trusted OS and the UART port ID to be used. The Tegra 73 memory controller driver programs this base/size in order to restrict NS 74 accesses. 75 76 typedef struct plat\_params\_from\_bl2 { 77 /\* TZ memory size */ 78 uint64\_t tzdram\_size; 79 /* TZ memory base */ 80 uint64\_t tzdram\_base; 81 /* UART port ID \*/ 82 int uart\_id; 83 } plat\_params\_from\_bl2\_t; 84 85 Power Management 86 ================ 87 88 The PSCI implementation expects each platform to expose the 'power state' 89 parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field 90 is implementation defined on Tegra SoCs and is preferably defined by 91 tegra\_def.h. 92 93 Tegra configs 94 ============= 95 96 - 'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity 97 Protection bit, for ARM Cortex-A57 CPUs, during CPU boot. This flag will 98 be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit. 99
