1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <debug.h> 9 #include <dw_ufs.h> 10 #include <mmio.h> 11 #include <stdint.h> 12 #include <string.h> 13 #include <ufs.h> 14 15 static int dwufs_phy_init(ufs_params_t *params) 16 { 17 uintptr_t base; 18 unsigned int fsm0, fsm1; 19 unsigned int data; 20 int result; 21 22 assert((params != NULL) && (params->reg_base != 0)); 23 24 base = params->reg_base; 25 26 /* Unipro VS_MPHY disable */ 27 ufshc_dme_set(VS_MPHY_DISABLE_OFFSET, 0, VS_MPHY_DISABLE_MPHYDIS); 28 ufshc_dme_set(PA_HS_SERIES_OFFSET, 0, 2); 29 /* MPHY CBRATESEL */ 30 ufshc_dme_set(0x8114, 0, 1); 31 /* MPHY CBOVRCTRL2 */ 32 ufshc_dme_set(0x8121, 0, 0x2d); 33 /* MPHY CBOVRCTRL3 */ 34 ufshc_dme_set(0x8122, 0, 0x1); 35 ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1); 36 37 /* MPHY RXOVRCTRL4 rx0 */ 38 ufshc_dme_set(0x800d, 4, 0x58); 39 /* MPHY RXOVRCTRL4 rx1 */ 40 ufshc_dme_set(0x800d, 5, 0x58); 41 /* MPHY RXOVRCTRL5 rx0 */ 42 ufshc_dme_set(0x800e, 4, 0xb); 43 /* MPHY RXOVRCTRL5 rx1 */ 44 ufshc_dme_set(0x800e, 5, 0xb); 45 /* MPHY RXSQCONTROL rx0 */ 46 ufshc_dme_set(0x8009, 4, 0x1); 47 /* MPHY RXSQCONTROL rx1 */ 48 ufshc_dme_set(0x8009, 5, 0x1); 49 ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1); 50 51 ufshc_dme_set(0x8113, 0, 0x1); 52 ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1); 53 54 ufshc_dme_set(RX_HS_G3_SYNC_LENGTH_CAP_OFFSET, 4, 0x4a); 55 ufshc_dme_set(RX_HS_G3_SYNC_LENGTH_CAP_OFFSET, 5, 0x4a); 56 ufshc_dme_set(RX_HS_G2_SYNC_LENGTH_CAP_OFFSET, 4, 0x4a); 57 ufshc_dme_set(RX_HS_G2_SYNC_LENGTH_CAP_OFFSET, 5, 0x4a); 58 ufshc_dme_set(RX_MIN_ACTIVATETIME_CAP_OFFSET, 4, 0x7); 59 ufshc_dme_set(RX_MIN_ACTIVATETIME_CAP_OFFSET, 5, 0x7); 60 ufshc_dme_set(TX_HIBERN8TIME_CAP_OFFSET, 0, 0x5); 61 ufshc_dme_set(TX_HIBERN8TIME_CAP_OFFSET, 1, 0x5); 62 ufshc_dme_set(VS_MPHY_CFG_UPDT_OFFSET, 0, 1); 63 64 result = ufshc_dme_get(VS_MPHY_DISABLE_OFFSET, 0, &data); 65 assert((result == 0) && (data == VS_MPHY_DISABLE_MPHYDIS)); 66 /* enable Unipro VS MPHY */ 67 ufshc_dme_set(VS_MPHY_DISABLE_OFFSET, 0, 0); 68 69 while (1) { 70 result = ufshc_dme_get(TX_FSM_STATE_OFFSET, 0, &fsm0); 71 assert(result == 0); 72 result = ufshc_dme_get(TX_FSM_STATE_OFFSET, 1, &fsm1); 73 assert(result == 0); 74 if ((fsm0 == TX_FSM_STATE_HIBERN8) && 75 (fsm1 == TX_FSM_STATE_HIBERN8)) 76 break; 77 } 78 79 mmio_write_32(base + HCLKDIV, 0xE4); 80 mmio_clrbits_32(base + AHIT, 0x3FF); 81 82 ufshc_dme_set(PA_LOCAL_TX_LCC_ENABLE_OFFSET, 0, 0); 83 ufshc_dme_set(VS_MK2_EXTN_SUPPORT_OFFSET, 0, 0); 84 85 result = ufshc_dme_get(VS_MK2_EXTN_SUPPORT_OFFSET, 0, &data); 86 assert((result == 0) && (data == 0)); 87 88 ufshc_dme_set(DL_AFC0_CREDIT_THRESHOLD_OFFSET, 0, 0); 89 ufshc_dme_set(DL_TC0_OUT_ACK_THRESHOLD_OFFSET, 0, 0); 90 ufshc_dme_set(DL_TC0_TX_FC_THRESHOLD_OFFSET, 0, 9); 91 (void)result; 92 return 0; 93 } 94 95 static int dwufs_phy_set_pwr_mode(ufs_params_t *params) 96 { 97 int result; 98 unsigned int data, tx_lanes, rx_lanes; 99 uintptr_t base; 100 101 assert((params != NULL) && (params->reg_base != 0)); 102 103 base = params->reg_base; 104 105 result = ufshc_dme_get(PA_TACTIVATE_OFFSET, 0, &data); 106 assert(result == 0); 107 if (data < 7) { 108 result = ufshc_dme_set(PA_TACTIVATE_OFFSET, 0, 7); 109 assert(result == 0); 110 } 111 result = ufshc_dme_get(PA_CONNECTED_TX_DATA_LANES_OFFSET, 0, &tx_lanes); 112 assert(result == 0); 113 result = ufshc_dme_get(PA_CONNECTED_RX_DATA_LANES_OFFSET, 0, &rx_lanes); 114 assert(result == 0); 115 116 result = ufshc_dme_set(PA_TX_SKIP_OFFSET, 0, 0); 117 assert(result == 0); 118 result = ufshc_dme_set(PA_TX_GEAR_OFFSET, 0, 3); 119 assert(result == 0); 120 result = ufshc_dme_set(PA_RX_GEAR_OFFSET, 0, 3); 121 assert(result == 0); 122 result = ufshc_dme_set(PA_HS_SERIES_OFFSET, 0, 2); 123 assert(result == 0); 124 result = ufshc_dme_set(PA_TX_TERMINATION_OFFSET, 0, 1); 125 assert(result == 0); 126 result = ufshc_dme_set(PA_RX_TERMINATION_OFFSET, 0, 1); 127 assert(result == 0); 128 result = ufshc_dme_set(PA_SCRAMBLING_OFFSET, 0, 0); 129 assert(result == 0); 130 result = ufshc_dme_set(PA_ACTIVE_TX_DATA_LANES_OFFSET, 0, tx_lanes); 131 assert(result == 0); 132 result = ufshc_dme_set(PA_ACTIVE_RX_DATA_LANES_OFFSET, 0, rx_lanes); 133 assert(result == 0); 134 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA0_OFFSET, 0, 8191); 135 assert(result == 0); 136 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA1_OFFSET, 0, 65535); 137 assert(result == 0); 138 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA2_OFFSET, 0, 32767); 139 assert(result == 0); 140 result = ufshc_dme_set(DME_FC0_PROTECTION_TIMEOUT_OFFSET, 0, 8191); 141 assert(result == 0); 142 result = ufshc_dme_set(DME_TC0_REPLAY_TIMEOUT_OFFSET, 0, 65535); 143 assert(result == 0); 144 result = ufshc_dme_set(DME_AFC0_REQ_TIMEOUT_OFFSET, 0, 32767); 145 assert(result == 0); 146 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA3_OFFSET, 0, 8191); 147 assert(result == 0); 148 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA4_OFFSET, 0, 65535); 149 assert(result == 0); 150 result = ufshc_dme_set(PA_PWR_MODE_USER_DATA5_OFFSET, 0, 32767); 151 assert(result == 0); 152 result = ufshc_dme_set(DME_FC1_PROTECTION_TIMEOUT_OFFSET, 0, 8191); 153 assert(result == 0); 154 result = ufshc_dme_set(DME_TC1_REPLAY_TIMEOUT_OFFSET, 0, 65535); 155 assert(result == 0); 156 result = ufshc_dme_set(DME_AFC1_REQ_TIMEOUT_OFFSET, 0, 32767); 157 assert(result == 0); 158 159 result = ufshc_dme_set(PA_PWR_MODE_OFFSET, 0, 0x11); 160 assert(result == 0); 161 do { 162 data = mmio_read_32(base + IS); 163 } while ((data & UFS_INT_UPMS) == 0); 164 mmio_write_32(base + IS, UFS_INT_UPMS); 165 data = mmio_read_32(base + HCS); 166 if ((data & HCS_UPMCRS_MASK) == HCS_PWR_LOCAL) 167 INFO("ufs: change power mode success\n"); 168 else 169 WARN("ufs: HCS.UPMCRS error, HCS:0x%x\n", data); 170 (void)result; 171 return 0; 172 } 173 174 const ufs_ops_t dw_ufs_ops = { 175 .phy_init = dwufs_phy_init, 176 .phy_set_pwr_mode = dwufs_phy_set_pwr_mode, 177 }; 178 179 int dw_ufs_init(dw_ufs_params_t *params) 180 { 181 ufs_params_t ufs_params; 182 183 memset(&ufs_params, 0, sizeof(ufs_params)); 184 ufs_params.reg_base = params->reg_base; 185 ufs_params.desc_base = params->desc_base; 186 ufs_params.desc_size = params->desc_size; 187 ufs_params.flags = params->flags; 188 ufs_init(&dw_ufs_ops, &ufs_params); 189 return 0; 190 } 191
