1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <smcc_helpers.h> 16 #include <string.h> 17 #include <utils.h> 18 19 /******************************************************************************* 20 * Context management library initialisation routine. This library is used by 21 * runtime services to share pointers to 'cpu_context' structures for the secure 22 * and non-secure states. Management of the structures and their associated 23 * memory is not done by the context management library e.g. the PSCI service 24 * manages the cpu context used for entry from and exit to the non-secure state. 25 * The Secure payload manages the context(s) corresponding to the secure state. 26 * It also uses this library to get access to the non-secure 27 * state cpu context pointers. 28 ******************************************************************************/ 29 void cm_init(void) 30 { 31 /* 32 * The context management library has only global data to initialize, but 33 * that will be done when the BSS is zeroed out 34 */ 35 } 36 37 /******************************************************************************* 38 * The following function initializes the cpu_context 'ctx' for 39 * first use, and sets the initial entrypoint state as specified by the 40 * entry_point_info structure. 41 * 42 * The security state to initialize is determined by the SECURE attribute 43 * of the entry_point_info. The function returns a pointer to the initialized 44 * context and sets this as the next context to return to. 45 * 46 * The EE and ST attributes are used to configure the endianness and secure 47 * timer availability for the new execution context. 48 * 49 * To prepare the register state for entry call cm_prepare_el3_exit() and 50 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 51 * cm_e1_sysreg_context_restore(). 52 ******************************************************************************/ 53 static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 54 { 55 unsigned int security_state; 56 uint32_t scr, sctlr; 57 regs_t *reg_ctx; 58 59 assert(ctx); 60 61 security_state = GET_SECURITY_STATE(ep->h.attr); 62 63 /* Clear any residual register values from the context */ 64 zeromem(ctx, sizeof(*ctx)); 65 66 reg_ctx = get_regs_ctx(ctx); 67 68 /* 69 * Base the context SCR on the current value, adjust for entry point 70 * specific requirements 71 */ 72 scr = read_scr(); 73 scr &= ~(SCR_NS_BIT | SCR_HCE_BIT); 74 75 if (security_state != SECURE) 76 scr |= SCR_NS_BIT; 77 78 if (security_state != SECURE) { 79 /* 80 * Set up SCTLR for the Non-secure context. 81 * 82 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 83 * 84 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 85 * required by PSCI specification) 86 * 87 * Set remaining SCTLR fields to their architecturally defined 88 * values. Some fields reset to an IMPLEMENTATION DEFINED value: 89 * 90 * SCTLR.TE: Set to zero so that exceptions to an Exception 91 * Level executing at PL1 are taken to A32 state. 92 * 93 * SCTLR.V: Set to zero to select the normal exception vectors 94 * with base address held in VBAR. 95 */ 96 assert(((ep->spsr >> SPSR_E_SHIFT) & SPSR_E_MASK) == 97 (EP_GET_EE(ep->h.attr) >> EP_EE_SHIFT)); 98 99 sctlr = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 100 sctlr |= (SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_V_BIT)); 101 write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr); 102 } 103 104 /* 105 * The target exception level is based on the spsr mode requested. If 106 * execution is requested to hyp mode, HVC is enabled via SCR.HCE. 107 */ 108 if (GET_M32(ep->spsr) == MODE32_hyp) 109 scr |= SCR_HCE_BIT; 110 111 /* 112 * Store the initialised values for SCTLR and SCR in the cpu_context. 113 * The Hyp mode registers are not part of the saved context and are 114 * set-up in cm_prepare_el3_exit(). 115 */ 116 write_ctx_reg(reg_ctx, CTX_SCR, scr); 117 write_ctx_reg(reg_ctx, CTX_LR, ep->pc); 118 write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr); 119 120 /* 121 * Store the r0-r3 value from the entrypoint into the context 122 * Use memcpy as we are in control of the layout of the structures 123 */ 124 memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t)); 125 } 126 127 /******************************************************************************* 128 * The following function initializes the cpu_context for a CPU specified by 129 * its `cpu_idx` for first use, and sets the initial entrypoint state as 130 * specified by the entry_point_info structure. 131 ******************************************************************************/ 132 void cm_init_context_by_index(unsigned int cpu_idx, 133 const entry_point_info_t *ep) 134 { 135 cpu_context_t *ctx; 136 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 137 cm_init_context_common(ctx, ep); 138 } 139 140 /******************************************************************************* 141 * The following function initializes the cpu_context for the current CPU 142 * for first use, and sets the initial entrypoint state as specified by the 143 * entry_point_info structure. 144 ******************************************************************************/ 145 void cm_init_my_context(const entry_point_info_t *ep) 146 { 147 cpu_context_t *ctx; 148 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 149 cm_init_context_common(ctx, ep); 150 } 151 152 /******************************************************************************* 153 * Prepare the CPU system registers for first entry into secure or normal world 154 * 155 * If execution is requested to hyp mode, HSCTLR is initialized 156 * If execution is requested to non-secure PL1, and the CPU supports 157 * HYP mode then HYP mode is disabled by configuring all necessary HYP mode 158 * registers. 159 ******************************************************************************/ 160 void cm_prepare_el3_exit(uint32_t security_state) 161 { 162 uint32_t hsctlr, scr; 163 cpu_context_t *ctx = cm_get_context(security_state); 164 165 assert(ctx); 166 167 if (security_state == NON_SECURE) { 168 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); 169 if (scr & SCR_HCE_BIT) { 170 /* Use SCTLR value to initialize HSCTLR */ 171 hsctlr = read_ctx_reg(get_regs_ctx(ctx), 172 CTX_NS_SCTLR); 173 hsctlr |= HSCTLR_RES1; 174 /* Temporarily set the NS bit to access HSCTLR */ 175 write_scr(read_scr() | SCR_NS_BIT); 176 /* 177 * Make sure the write to SCR is complete so that 178 * we can access HSCTLR 179 */ 180 isb(); 181 write_hsctlr(hsctlr); 182 isb(); 183 184 write_scr(read_scr() & ~SCR_NS_BIT); 185 isb(); 186 } else if (read_id_pfr1() & 187 (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) { 188 /* 189 * Set the NS bit to access NS copies of certain banked 190 * registers 191 */ 192 write_scr(read_scr() | SCR_NS_BIT); 193 isb(); 194 195 /* 196 * Hyp / PL2 present but unused, need to disable safely. 197 * HSCTLR can be ignored in this case. 198 * 199 * Set HCR to its architectural reset value so that 200 * Non-secure operations do not trap to Hyp mode. 201 */ 202 write_hcr(HCR_RESET_VAL); 203 204 /* 205 * Set HCPTR to its architectural reset value so that 206 * Non-secure access from EL1 or EL0 to trace and to 207 * Advanced SIMD and floating point functionality does 208 * not trap to Hyp mode. 209 */ 210 write_hcptr(HCPTR_RESET_VAL); 211 212 /* 213 * Initialise CNTHCTL. All fields are architecturally 214 * UNKNOWN on reset and are set to zero except for 215 * field(s) listed below. 216 * 217 * CNTHCTL.PL1PCEN: Disable traps to Hyp mode of 218 * Non-secure EL0 and EL1 accessed to the physical 219 * timer registers. 220 * 221 * CNTHCTL.PL1PCTEN: Disable traps to Hyp mode of 222 * Non-secure EL0 and EL1 accessed to the physical 223 * counter registers. 224 */ 225 write_cnthctl(CNTHCTL_RESET_VAL | 226 PL1PCEN_BIT | PL1PCTEN_BIT); 227 228 /* 229 * Initialise CNTVOFF to zero as it resets to an 230 * IMPLEMENTATION DEFINED value. 231 */ 232 write64_cntvoff(0); 233 234 /* 235 * Set VPIDR and VMPIDR to match MIDR_EL1 and MPIDR 236 * respectively. 237 */ 238 write_vpidr(read_midr()); 239 write_vmpidr(read_mpidr()); 240 241 /* 242 * Initialise VTTBR, setting all fields rather than 243 * relying on the hw. Some fields are architecturally 244 * UNKNOWN at reset. 245 * 246 * VTTBR.VMID: Set to zero which is the architecturally 247 * defined reset value. Even though EL1&0 stage 2 248 * address translation is disabled, cache maintenance 249 * operations depend on the VMID. 250 * 251 * VTTBR.BADDR: Set to zero as EL1&0 stage 2 address 252 * translation is disabled. 253 */ 254 write64_vttbr(VTTBR_RESET_VAL & 255 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 256 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 257 258 /* 259 * Initialise HDCR, setting all the fields rather than 260 * relying on hw. 261 * 262 * HDCR.HPMN: Set to value of PMCR.N which is the 263 * architecturally-defined reset value. 264 */ 265 write_hdcr(HDCR_RESET_VAL | 266 ((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT)); 267 268 /* 269 * Set HSTR to its architectural reset value so that 270 * access to system registers in the cproc=1111 271 * encoding space do not trap to Hyp mode. 272 */ 273 write_hstr(HSTR_RESET_VAL); 274 /* 275 * Set CNTHP_CTL to its architectural reset value to 276 * disable the EL2 physical timer and prevent timer 277 * interrupts. Some fields are architecturally UNKNOWN 278 * on reset and are set to zero. 279 */ 280 write_cnthp_ctl(CNTHP_CTL_RESET_VAL); 281 isb(); 282 283 write_scr(read_scr() & ~SCR_NS_BIT); 284 isb(); 285 } 286 } 287 } 288
