1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <cci.h> 11 #include <ccn.h> 12 #include <debug.h> 13 #include <gicv2.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <v2m_def.h> 17 #include "../fvp_def.h" 18 19 /* Defines for GIC Driver build time selection */ 20 #define FVP_GICV2 1 21 #define FVP_GICV3 2 22 #define FVP_GICV3_LEGACY 3 23 24 /******************************************************************************* 25 * arm_config holds the characteristics of the differences between the three FVP 26 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 27 * at each boot stage by the primary before enabling the MMU (to allow 28 * interconnect configuration) & used thereafter. Each BL will have its own copy 29 * to allow independent operation. 30 ******************************************************************************/ 31 arm_config_t arm_config; 32 33 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 34 DEVICE0_SIZE, \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 38 DEVICE1_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 /* 42 * Need to be mapped with write permissions in order to set a new non-volatile 43 * counter value. 44 */ 45 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 46 DEVICE2_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 50 /* 51 * Table of memory regions for various BL stages to map using the MMU. 52 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 53 * takes care of mapping it. 54 * 55 * The flash needs to be mapped as writable in order to erase the FIP's Table of 56 * Contents in case of unrecoverable error (see plat_error_handler()). 57 */ 58 #ifdef IMAGE_BL1 59 const mmap_region_t plat_arm_mmap[] = { 60 ARM_MAP_SHARED_RAM, 61 V2M_MAP_FLASH0_RW, 62 V2M_MAP_IOFPGA, 63 MAP_DEVICE0, 64 MAP_DEVICE1, 65 #if TRUSTED_BOARD_BOOT 66 /* To access the Root of Trust Public Key registers. */ 67 MAP_DEVICE2, 68 /* Map DRAM to authenticate NS_BL2U image. */ 69 ARM_MAP_NS_DRAM1, 70 #endif 71 {0} 72 }; 73 #endif 74 #ifdef IMAGE_BL2 75 const mmap_region_t plat_arm_mmap[] = { 76 ARM_MAP_SHARED_RAM, 77 V2M_MAP_FLASH0_RW, 78 V2M_MAP_IOFPGA, 79 MAP_DEVICE0, 80 MAP_DEVICE1, 81 ARM_MAP_NS_DRAM1, 82 #ifdef AARCH64 83 ARM_MAP_DRAM2, 84 #endif 85 #ifdef SPD_tspd 86 ARM_MAP_TSP_SEC_MEM, 87 #endif 88 #if TRUSTED_BOARD_BOOT 89 /* To access the Root of Trust Public Key registers. */ 90 MAP_DEVICE2, 91 #endif 92 #if ARM_BL31_IN_DRAM 93 ARM_MAP_BL31_SEC_DRAM, 94 #endif 95 #ifdef SPD_opteed 96 ARM_MAP_OPTEE_CORE_MEM, 97 ARM_OPTEE_PAGEABLE_LOAD_MEM, 98 #endif 99 {0} 100 }; 101 #endif 102 #ifdef IMAGE_BL2U 103 const mmap_region_t plat_arm_mmap[] = { 104 MAP_DEVICE0, 105 V2M_MAP_IOFPGA, 106 {0} 107 }; 108 #endif 109 #ifdef IMAGE_BL31 110 const mmap_region_t plat_arm_mmap[] = { 111 ARM_MAP_SHARED_RAM, 112 ARM_MAP_EL3_TZC_DRAM, 113 V2M_MAP_IOFPGA, 114 MAP_DEVICE0, 115 MAP_DEVICE1, 116 ARM_V2M_MAP_MEM_PROTECT, 117 {0} 118 }; 119 #endif 120 #ifdef IMAGE_BL32 121 const mmap_region_t plat_arm_mmap[] = { 122 #ifdef AARCH32 123 ARM_MAP_SHARED_RAM, 124 #endif 125 V2M_MAP_IOFPGA, 126 MAP_DEVICE0, 127 MAP_DEVICE1, 128 {0} 129 }; 130 #endif 131 132 ARM_CASSERT_MMAP 133 134 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 135 static const int fvp_cci400_map[] = { 136 PLAT_FVP_CCI400_CLUS0_SL_PORT, 137 PLAT_FVP_CCI400_CLUS1_SL_PORT, 138 }; 139 140 static const int fvp_cci5xx_map[] = { 141 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 142 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 143 }; 144 145 static unsigned int get_interconnect_master(void) 146 { 147 unsigned int master; 148 u_register_t mpidr; 149 150 mpidr = read_mpidr_el1(); 151 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 152 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 153 154 assert(master < FVP_CLUSTER_COUNT); 155 return master; 156 } 157 #endif 158 159 /******************************************************************************* 160 * A single boot loader stack is expected to work on both the Foundation FVP 161 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 162 * SYS_ID register provides a mechanism for detecting the differences between 163 * these platforms. This information is stored in a per-BL array to allow the 164 * code to take the correct path.Per BL platform configuration. 165 ******************************************************************************/ 166 void fvp_config_setup(void) 167 { 168 unsigned int rev, hbi, bld, arch, sys_id; 169 170 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 171 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 172 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 173 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 174 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 175 176 if (arch != ARCH_MODEL) { 177 ERROR("This firmware is for FVP models\n"); 178 panic(); 179 } 180 181 /* 182 * The build field in the SYS_ID tells which variant of the GIC 183 * memory is implemented by the model. 184 */ 185 switch (bld) { 186 case BLD_GIC_VE_MMAP: 187 ERROR("Legacy Versatile Express memory map for GIC peripheral" 188 " is not supported\n"); 189 panic(); 190 break; 191 case BLD_GIC_A53A57_MMAP: 192 break; 193 default: 194 ERROR("Unsupported board build %x\n", bld); 195 panic(); 196 } 197 198 /* 199 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 200 * for the Foundation FVP. 201 */ 202 switch (hbi) { 203 case HBI_FOUNDATION_FVP: 204 arm_config.flags = 0; 205 206 /* 207 * Check for supported revisions of Foundation FVP 208 * Allow future revisions to run but emit warning diagnostic 209 */ 210 switch (rev) { 211 case REV_FOUNDATION_FVP_V2_0: 212 case REV_FOUNDATION_FVP_V2_1: 213 case REV_FOUNDATION_FVP_v9_1: 214 case REV_FOUNDATION_FVP_v9_6: 215 break; 216 default: 217 WARN("Unrecognized Foundation FVP revision %x\n", rev); 218 break; 219 } 220 break; 221 case HBI_BASE_FVP: 222 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 223 224 /* 225 * Check for supported revisions 226 * Allow future revisions to run but emit warning diagnostic 227 */ 228 switch (rev) { 229 case REV_BASE_FVP_V0: 230 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 231 break; 232 case REV_BASE_FVP_REVC: 233 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 234 ARM_CONFIG_FVP_HAS_CCI5XX); 235 break; 236 default: 237 WARN("Unrecognized Base FVP revision %x\n", rev); 238 break; 239 } 240 break; 241 default: 242 ERROR("Unsupported board HBI number 0x%x\n", hbi); 243 panic(); 244 } 245 246 /* 247 * We assume that the presence of MT bit, and therefore shifted 248 * affinities, is uniform across the platform: either all CPUs, or no 249 * CPUs implement it. 250 */ 251 if (read_mpidr_el1() & MPIDR_MT_MASK) 252 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 253 } 254 255 256 void fvp_interconnect_init(void) 257 { 258 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 259 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 260 ERROR("Unrecognized CCN variant detected. Only CCN-502" 261 " is supported"); 262 panic(); 263 } 264 265 plat_arm_interconnect_init(); 266 #else 267 uintptr_t cci_base = 0; 268 const int *cci_map = 0; 269 unsigned int map_size = 0; 270 271 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 272 ARM_CONFIG_FVP_HAS_CCI5XX))) { 273 return; 274 } 275 276 /* Initialize the right interconnect */ 277 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 278 cci_base = PLAT_FVP_CCI5XX_BASE; 279 cci_map = fvp_cci5xx_map; 280 map_size = ARRAY_SIZE(fvp_cci5xx_map); 281 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 282 cci_base = PLAT_FVP_CCI400_BASE; 283 cci_map = fvp_cci400_map; 284 map_size = ARRAY_SIZE(fvp_cci400_map); 285 } 286 287 assert(cci_base); 288 assert(cci_map); 289 cci_init(cci_base, cci_map, map_size); 290 #endif 291 } 292 293 void fvp_interconnect_enable(void) 294 { 295 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 296 plat_arm_interconnect_enter_coherency(); 297 #else 298 unsigned int master; 299 300 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 301 ARM_CONFIG_FVP_HAS_CCI5XX)) { 302 master = get_interconnect_master(); 303 cci_enable_snoop_dvm_reqs(master); 304 } 305 #endif 306 } 307 308 void fvp_interconnect_disable(void) 309 { 310 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 311 plat_arm_interconnect_exit_coherency(); 312 #else 313 unsigned int master; 314 315 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 316 ARM_CONFIG_FVP_HAS_CCI5XX)) { 317 master = get_interconnect_master(); 318 cci_disable_snoop_dvm_reqs(master); 319 } 320 #endif 321 } 322
