1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __FVP_DEF_H__ 8 #define __FVP_DEF_H__ 9 10 #ifndef FVP_CLUSTER_COUNT 11 #define FVP_CLUSTER_COUNT 2 12 #endif 13 #define FVP_MAX_CPUS_PER_CLUSTER 4 14 15 #ifndef FVP_MAX_PE_PER_CPU 16 # define FVP_MAX_PE_PER_CPU 1 17 #endif 18 19 #define FVP_PRIMARY_CPU 0x0 20 21 /* Defines for the Interconnect build selection */ 22 #define FVP_CCI 1 23 #define FVP_CCN 2 24 25 /******************************************************************************* 26 * FVP memory map related constants 27 ******************************************************************************/ 28 29 #define FLASH1_BASE 0x0c000000 30 #define FLASH1_SIZE 0x04000000 31 32 #define PSRAM_BASE 0x14000000 33 #define PSRAM_SIZE 0x04000000 34 35 #define VRAM_BASE 0x18000000 36 #define VRAM_SIZE 0x02000000 37 38 /* Aggregate of all devices in the first GB */ 39 #define DEVICE0_BASE 0x20000000 40 #define DEVICE0_SIZE 0x0c200000 41 42 /* 43 * In case of FVP models with CCN, the CCN register space overlaps into 44 * the NSRAM area. 45 */ 46 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 47 #define DEVICE1_BASE 0x2e000000 48 #define DEVICE1_SIZE 0x1A00000 49 #else 50 #define DEVICE1_BASE 0x2f000000 51 #define DEVICE1_SIZE 0x200000 52 #define NSRAM_BASE 0x2e000000 53 #define NSRAM_SIZE 0x10000 54 #endif 55 /* Devices in the second GB */ 56 #define DEVICE2_BASE 0x7fe00000 57 #define DEVICE2_SIZE 0x00200000 58 59 #define PCIE_EXP_BASE 0x40000000 60 #define TZRNG_BASE 0x7fe60000 61 62 /* Non-volatile counters */ 63 #define TRUSTED_NVCTR_BASE 0x7fe70000 64 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000) 65 #define TFW_NVCTR_SIZE 4 66 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004) 67 #define NTFW_CTR_SIZE 4 68 69 /* Keys */ 70 #define SOC_KEYS_BASE 0x7fe80000 71 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 72 #define TZ_PUB_KEY_HASH_SIZE 32 73 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 74 #define HU_KEY_SIZE 16 75 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 76 #define END_KEY_SIZE 32 77 78 /* Constants to distinguish FVP type */ 79 #define HBI_BASE_FVP 0x020 80 #define REV_BASE_FVP_V0 0x0 81 #define REV_BASE_FVP_REVC 0x2 82 83 #define HBI_FOUNDATION_FVP 0x010 84 #define REV_FOUNDATION_FVP_V2_0 0x0 85 #define REV_FOUNDATION_FVP_V2_1 0x1 86 #define REV_FOUNDATION_FVP_v9_1 0x2 87 #define REV_FOUNDATION_FVP_v9_6 0x3 88 89 #define BLD_GIC_VE_MMAP 0x0 90 #define BLD_GIC_A53A57_MMAP 0x1 91 92 #define ARCH_MODEL 0x1 93 94 /* FVP Power controller base address*/ 95 #define PWRC_BASE 0x1c100000 96 97 /* FVP SP804 timer frequency is 35 MHz*/ 98 #define SP804_TIMER_CLKMULT 1 99 #define SP804_TIMER_CLKDIV 35 100 101 /* SP810 controller. FVP specific flags */ 102 #define FVP_SP810_CTRL_TIM0_OV (1 << 16) 103 #define FVP_SP810_CTRL_TIM1_OV (1 << 18) 104 #define FVP_SP810_CTRL_TIM2_OV (1 << 20) 105 #define FVP_SP810_CTRL_TIM3_OV (1 << 22) 106 107 /******************************************************************************* 108 * GIC-400 & interrupt handling related constants 109 ******************************************************************************/ 110 /* VE compatible GIC memory map */ 111 #define VE_GICD_BASE 0x2c001000 112 #define VE_GICC_BASE 0x2c002000 113 #define VE_GICH_BASE 0x2c004000 114 #define VE_GICV_BASE 0x2c006000 115 116 /* Base FVP compatible GIC memory map */ 117 #define BASE_GICD_BASE 0x2f000000 118 #define BASE_GICR_BASE 0x2f100000 119 #define BASE_GICC_BASE 0x2c000000 120 #define BASE_GICH_BASE 0x2c010000 121 #define BASE_GICV_BASE 0x2c02f000 122 123 #define FVP_IRQ_TZ_WDOG 56 124 #define FVP_IRQ_SEC_SYS_TIMER 57 125 126 127 /******************************************************************************* 128 * TrustZone address space controller related constants 129 ******************************************************************************/ 130 131 /* NSAIDs used by devices in TZC filter 0 on FVP */ 132 #define FVP_NSAID_DEFAULT 0 133 #define FVP_NSAID_PCI 1 134 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 135 #define FVP_NSAID_AP 9 /* Application Processors */ 136 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 137 138 /* NSAIDs used by devices in TZC filter 2 on FVP */ 139 #define FVP_NSAID_HDLCD0 2 140 #define FVP_NSAID_CLCD 7 141 142 #endif /* __FVP_DEF_H__ */ 143
