1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <arm_gic.h> 8 #include <bl_common.h> 9 #include <cci.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <mmio.h> 13 #include <mtk_plat_common.h> 14 #include <mtk_sip_svc.h> 15 #include <plat_private.h> 16 #include <platform.h> 17 #include <xlat_tables.h> 18 19 struct atf_arg_t gteearg; 20 21 void clean_top_32b_of_param(uint32_t smc_fid, 22 uint64_t *px1, 23 uint64_t *px2, 24 uint64_t *px3, 25 uint64_t *px4) 26 { 27 /* if parameters from SMC32. Clean top 32 bits */ 28 if (0 == (smc_fid & SMC_AARCH64_BIT)) { 29 *px1 = *px1 & SMC32_PARAM_MASK; 30 *px2 = *px2 & SMC32_PARAM_MASK; 31 *px3 = *px3 & SMC32_PARAM_MASK; 32 *px4 = *px4 & SMC32_PARAM_MASK; 33 } 34 } 35 36 #if MTK_SIP_KERNEL_BOOT_ENABLE 37 static struct kernel_info k_info; 38 39 static void save_kernel_info(uint64_t pc, 40 uint64_t r0, 41 uint64_t r1, 42 uint64_t k32_64) 43 { 44 k_info.k32_64 = k32_64; 45 k_info.pc = pc; 46 47 if (LINUX_KERNEL_32 == k32_64) { 48 /* for 32 bits kernel */ 49 k_info.r0 = 0; 50 /* machtype */ 51 k_info.r1 = r0; 52 /* tags */ 53 k_info.r2 = r1; 54 } else { 55 /* for 64 bits kernel */ 56 k_info.r0 = r0; 57 k_info.r1 = r1; 58 } 59 } 60 61 uint64_t get_kernel_info_pc(void) 62 { 63 return k_info.pc; 64 } 65 66 uint64_t get_kernel_info_r0(void) 67 { 68 return k_info.r0; 69 } 70 71 uint64_t get_kernel_info_r1(void) 72 { 73 return k_info.r1; 74 } 75 76 uint64_t get_kernel_info_r2(void) 77 { 78 return k_info.r2; 79 } 80 81 void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4) 82 { 83 static uint8_t kernel_boot_once_flag; 84 /* only support in booting flow */ 85 if (0 == kernel_boot_once_flag) { 86 kernel_boot_once_flag = 1; 87 88 console_init(gteearg.atf_log_port, 89 UART_CLOCK, UART_BAUDRATE); 90 INFO("save kernel info\n"); 91 save_kernel_info(x1, x2, x3, x4); 92 bl31_prepare_kernel_entry(x4); 93 INFO("el3_exit\n"); 94 console_uninit(); 95 } 96 } 97 #endif 98 99 uint32_t plat_get_spsr_for_bl33_entry(void) 100 { 101 unsigned int mode; 102 uint32_t spsr; 103 unsigned int ee; 104 unsigned long daif; 105 106 INFO("Secondary bootloader is AArch32\n"); 107 mode = MODE32_svc; 108 ee = 0; 109 /* 110 * TODO: Choose async. exception bits if HYP mode is not 111 * implemented according to the values of SCR.{AW, FW} bits 112 */ 113 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; 114 115 spsr = SPSR_MODE32(mode, 0, ee, daif); 116 return spsr; 117 } 118