1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <arm_gic.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <cci.h> 11 #include <common_def.h> 12 #include <console.h> 13 #include <context_mgmt.h> 14 #include <debug.h> 15 #include <generic_delay_timer.h> 16 #include <mcucfg.h> 17 #include <mmio.h> 18 #include <mt_cpuxgpt.h> 19 #include <mtk_plat_common.h> 20 #include <mtk_sip_svc.h> 21 #include <plat_private.h> 22 #include <platform.h> 23 #include <string.h> 24 #include <xlat_tables.h> 25 /******************************************************************************* 26 * Declarations of linker defined symbols which will help us find the layout 27 * of trusted SRAM 28 ******************************************************************************/ 29 unsigned long __RO_START__; 30 unsigned long __RO_END__; 31 32 /* 33 * The next 2 constants identify the extents of the code & RO data region. 34 * These addresses are used by the MMU setup code and therefore they must be 35 * page-aligned. It is the responsibility of the linker script to ensure that 36 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 37 */ 38 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 39 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 40 41 /* 42 * Placeholder variables for copying the arguments that have been passed to 43 * BL3-1 from BL2. 44 */ 45 static entry_point_info_t bl32_image_ep_info; 46 static entry_point_info_t bl33_image_ep_info; 47 48 static const int cci_map[] = { 49 PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX, 50 PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 51 }; 52 53 static uint32_t cci_map_length = ARRAY_SIZE(cci_map); 54 55 /* Table of regions to map using the MMU. */ 56 static const mmap_region_t plat_mmap[] = { 57 /* for TF text, RO, RW */ 58 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, 61 MT_DEVICE | MT_RW | MT_SECURE), 62 MAP_REGION_FLAT(RAM_CONSOLE_BASE & ~(PAGE_SIZE_MASK), RAM_CONSOLE_SIZE, 63 MT_DEVICE | MT_RW | MT_NS), 64 { 0 } 65 66 }; 67 68 /******************************************************************************* 69 * Macro generating the code for the function setting up the pagetables as per 70 * the platform memory map & initialize the mmu, for the given exception level 71 ******************************************************************************/ 72 #define DEFINE_CONFIGURE_MMU_EL(_el) \ 73 void plat_configure_mmu_el ## _el(unsigned long total_base, \ 74 unsigned long total_size, \ 75 unsigned long ro_start, \ 76 unsigned long ro_limit, \ 77 unsigned long coh_start, \ 78 unsigned long coh_limit) \ 79 { \ 80 mmap_add_region(total_base, total_base, \ 81 total_size, \ 82 MT_MEMORY | MT_RW | MT_SECURE); \ 83 mmap_add_region(ro_start, ro_start, \ 84 ro_limit - ro_start, \ 85 MT_MEMORY | MT_RO | MT_SECURE); \ 86 mmap_add_region(coh_start, coh_start, \ 87 coh_limit - coh_start, \ 88 MT_DEVICE | MT_RW | MT_SECURE); \ 89 mmap_add(plat_mmap); \ 90 init_xlat_tables(); \ 91 \ 92 enable_mmu_el ## _el(0); \ 93 } 94 95 /* Define EL3 variants of the function initialising the MMU */ 96 DEFINE_CONFIGURE_MMU_EL(3) 97 98 unsigned int plat_get_syscnt_freq2(void) 99 { 100 return SYS_COUNTER_FREQ_IN_TICKS; 101 } 102 103 void plat_cci_init(void) 104 { 105 /* Initialize CCI driver */ 106 cci_init(PLAT_MT_CCI_BASE, cci_map, cci_map_length); 107 } 108 109 void plat_cci_enable(void) 110 { 111 /* 112 * Enable CCI coherency for this cluster. 113 * No need for locks as no other cpu is active at the moment. 114 */ 115 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 116 } 117 118 void plat_cci_disable(void) 119 { 120 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 121 } 122 123 124 static void platform_setup_cpu(void) 125 { 126 /* setup big cores */ 127 mmio_write_32((uintptr_t)&mt6795_mcucfg->mp1_config_res, 128 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 129 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 130 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 131 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 132 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 133 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, MP1_AINACTS); 134 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_clkenm_div, 135 MP1_SW_CG_GEN); 136 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_rst_ctl, 137 MP1_L2RSTDISABLE); 138 139 /* set big cores arm64 boot mode */ 140 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_cpucfg, 141 MP1_CPUCFG_64BIT); 142 143 /* set LITTLE cores arm64 boot mode */ 144 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_rv_addr[0].rv_addr_hw, 145 MP0_CPUCFG_64BIT); 146 } 147 148 /******************************************************************************* 149 * Return a pointer to the 'entry_point_info' structure of the next image for 150 * the security state specified. BL33 corresponds to the non-secure image type 151 * while BL32 corresponds to the secure image type. A NULL pointer is returned 152 * if the image does not exist. 153 ******************************************************************************/ 154 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 155 { 156 entry_point_info_t *next_image_info; 157 158 next_image_info = (type == NON_SECURE) ? 159 &bl33_image_ep_info : &bl32_image_ep_info; 160 161 /* None of the images on this platform can have 0x0 as the entrypoint */ 162 if (next_image_info->pc) 163 return next_image_info; 164 else 165 return NULL; 166 } 167 168 /******************************************************************************* 169 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 170 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 171 * are lost (potentially). This needs to be done before the MMU is initialized 172 * so that the memory layout can be used while creating page tables. 173 * BL2 has flushed this information to memory, so we are guaranteed to pick up 174 * good data. 175 ******************************************************************************/ 176 void bl31_early_platform_setup(bl31_params_t *from_bl2, 177 void *plat_params_from_bl2) 178 { 179 struct mtk_bl_param_t *pmtk_bl_param = 180 (struct mtk_bl_param_t *)from_bl2; 181 struct atf_arg_t *teearg; 182 unsigned long long normal_base; 183 unsigned long long atf_base; 184 185 assert(from_bl2 != NULL); 186 /* 187 * Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits 188 * of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit 189 * to 64 bit state. So we need to clear high 32bit, 190 * which may be random value. 191 */ 192 pmtk_bl_param = 193 (struct mtk_bl_param_t *)((uint64_t)pmtk_bl_param & 0x00000000ffffffff); 194 plat_params_from_bl2 = 195 (void *)((uint64_t)plat_params_from_bl2 & 0x00000000ffffffff); 196 197 teearg = (struct atf_arg_t *)pmtk_bl_param->tee_info_addr; 198 199 console_init(teearg->atf_log_port, UART_CLOCK, UART_BAUDRATE); 200 memcpy((void *)>eearg, (void *)teearg, sizeof(struct atf_arg_t)); 201 202 normal_base = 0; 203 /* in ATF boot time, timer for cntpct_el0 is not initialized 204 * so it will not count now. 205 */ 206 atf_base = read_cntpct_el0(); 207 sched_clock_init(normal_base, atf_base); 208 209 VERBOSE("bl31_setup\n"); 210 211 /* Populate entry point information for BL3-2 and BL3-3 */ 212 SET_PARAM_HEAD(&bl32_image_ep_info, 213 PARAM_EP, 214 VERSION_1, 215 0); 216 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 217 bl32_image_ep_info.pc = BL32_BASE; 218 219 SET_PARAM_HEAD(&bl33_image_ep_info, 220 PARAM_EP, 221 VERSION_1, 222 0); 223 /* 224 * Tell BL3-1 where the non-trusted software image 225 * is located and the entry state information 226 */ 227 /* BL33_START_ADDRESS */ 228 bl33_image_ep_info.pc = pmtk_bl_param->bl33_start_addr; 229 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry(); 230 bl33_image_ep_info.args.arg4 = pmtk_bl_param->bootarg_loc; 231 bl33_image_ep_info.args.arg5 = pmtk_bl_param->bootarg_size; 232 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 233 } 234 /******************************************************************************* 235 * Perform any BL3-1 platform setup code 236 ******************************************************************************/ 237 238 void bl31_platform_setup(void) 239 { 240 platform_setup_cpu(); 241 242 generic_delay_timer_init(); 243 244 plat_mt_gic_driver_init(); 245 /* Initialize the gic cpu and distributor interfaces */ 246 plat_mt_gic_init(); 247 248 /* Topologies are best known to the platform. */ 249 mt_setup_topology(); 250 } 251 /******************************************************************************* 252 * Perform the very early platform specific architectural setup here. At the 253 * moment this is only intializes the mmu in a quick and dirty way. 254 * Init MTK propiartary log buffer control field. 255 ******************************************************************************/ 256 void bl31_plat_arch_setup(void) 257 { 258 /* Enable non-secure access to CCI-400 registers */ 259 mmio_write_32(CCI400_BASE + CCI_SEC_ACCESS_OFFSET, 0x1); 260 261 plat_cci_init(); 262 plat_cci_enable(); 263 264 if (gteearg.atf_log_buf_size != 0) { 265 INFO("mmap atf buffer : 0x%x, 0x%x\n\r", 266 gteearg.atf_log_buf_start, 267 gteearg.atf_log_buf_size); 268 269 mmap_add_region( 270 gteearg.atf_log_buf_start & 271 ~(PAGE_SIZE_2MB_MASK), 272 gteearg.atf_log_buf_start & 273 ~(PAGE_SIZE_2MB_MASK), 274 PAGE_SIZE_2MB, 275 MT_DEVICE | MT_RW | MT_NS); 276 277 INFO("mmap atf buffer (force 2MB aligned):0x%x, 0x%x\n", 278 (gteearg.atf_log_buf_start & ~(PAGE_SIZE_2MB_MASK)), 279 PAGE_SIZE_2MB); 280 } 281 /* 282 * add TZRAM_BASE to memory map 283 * then set RO and COHERENT to different attribute 284 */ 285 plat_configure_mmu_el3( 286 (TZRAM_BASE & ~(PAGE_SIZE_MASK)), 287 (TZRAM_SIZE & ~(PAGE_SIZE_MASK)), 288 (BL31_RO_BASE & ~(PAGE_SIZE_MASK)), 289 BL31_RO_LIMIT, 290 BL_COHERENT_RAM_BASE, 291 BL_COHERENT_RAM_END); 292 /* Initialize for ATF log buffer */ 293 if (gteearg.atf_log_buf_size != 0) { 294 gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE; 295 gteearg.atf_aee_debug_buf_start = 296 gteearg.atf_log_buf_start + 297 gteearg.atf_log_buf_size - ATF_AEE_BUFFER_SIZE; 298 INFO("ATF log service is registered (0x%x, aee:0x%x)\n", 299 gteearg.atf_log_buf_start, 300 gteearg.atf_aee_debug_buf_start); 301 } else{ 302 gteearg.atf_aee_debug_buf_size = 0; 303 gteearg.atf_aee_debug_buf_start = 0; 304 } 305 306 /* Platform code before bl31_main */ 307 /* compatible to the earlier chipset */ 308 309 /* Show to ATF log buffer & UART */ 310 INFO("BL3-1: %s\n", version_string); 311 INFO("BL3-1: %s\n", build_message); 312 313 } 314 #if 0 315 /* MTK Define */ 316 #define ACTLR_CPUECTLR_BIT (1 << 1) 317 318 void enable_ns_access_to_cpuectlr(void) 319 { 320 unsigned int next_actlr; 321 322 323 /* ACTLR_EL1 do not implement CUPECTLR */ 324 next_actlr = read_actlr_el2(); 325 next_actlr |= ACTLR_CPUECTLR_BIT; 326 write_actlr_el2(next_actlr); 327 328 next_actlr = read_actlr_el3(); 329 next_actlr |= ACTLR_CPUECTLR_BIT; 330 write_actlr_el3(next_actlr); 331 } 332 #endif 333 /******************************************************************************* 334 * This function prepare boot argument for 64 bit kernel entry 335 ******************************************************************************/ 336 static entry_point_info_t *bl31_plat_get_next_kernel64_ep_info(void) 337 { 338 entry_point_info_t *next_image_info; 339 unsigned int mode; 340 341 mode = 0; 342 343 /* Kernel image is always non-secured */ 344 next_image_info = &bl33_image_ep_info; 345 346 /* Figure out what mode we enter the non-secure world in */ 347 if (EL_IMPLEMENTED(2)) { 348 INFO("Kernel_EL2\n"); 349 mode = MODE_EL2; 350 } else{ 351 INFO("Kernel_EL1\n"); 352 mode = MODE_EL1; 353 } 354 355 INFO("Kernel is 64Bit\n"); 356 next_image_info->spsr = 357 SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 358 next_image_info->pc = get_kernel_info_pc(); 359 next_image_info->args.arg0 = get_kernel_info_r0(); 360 next_image_info->args.arg1 = get_kernel_info_r1(); 361 362 INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx\n", 363 next_image_info->pc, 364 next_image_info->args.arg0, 365 next_image_info->args.arg1); 366 367 368 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); 369 370 /* None of the images on this platform can have 0x0 as the entrypoint */ 371 if (next_image_info->pc) 372 return next_image_info; 373 else 374 return NULL; 375 } 376 377 /******************************************************************************* 378 * This function prepare boot argument for 32 bit kernel entry 379 ******************************************************************************/ 380 static entry_point_info_t *bl31_plat_get_next_kernel32_ep_info(void) 381 { 382 entry_point_info_t *next_image_info; 383 unsigned int mode; 384 385 mode = 0; 386 387 /* Kernel image is always non-secured */ 388 next_image_info = &bl33_image_ep_info; 389 390 /* Figure out what mode we enter the non-secure world in */ 391 mode = MODE32_hyp; 392 /* 393 * TODO: Consider the possibility of specifying the SPSR in 394 * the FIP ToC and allowing the platform to have a say as 395 * well. 396 */ 397 398 INFO("Kernel is 32Bit\n"); 399 next_image_info->spsr = 400 SPSR_MODE32(mode, SPSR_T_ARM, SPSR_E_LITTLE, 401 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT)); 402 next_image_info->pc = get_kernel_info_pc(); 403 next_image_info->args.arg0 = get_kernel_info_r0(); 404 next_image_info->args.arg1 = get_kernel_info_r1(); 405 next_image_info->args.arg2 = get_kernel_info_r2(); 406 407 INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx, r2=0x%lx\n", 408 next_image_info->pc, 409 next_image_info->args.arg0, 410 next_image_info->args.arg1, 411 next_image_info->args.arg2); 412 413 414 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); 415 416 /* None of the images on this platform can have 0x0 as the entrypoint */ 417 if (next_image_info->pc) 418 return next_image_info; 419 else 420 return NULL; 421 } 422 423 /******************************************************************************* 424 * This function prepare boot argument for kernel entrypoint 425 ******************************************************************************/ 426 void bl31_prepare_kernel_entry(uint64_t k32_64) 427 { 428 entry_point_info_t *next_image_info; 429 uint32_t image_type; 430 431 /* Determine which image to execute next */ 432 /* image_type = bl31_get_next_image_type(); */ 433 image_type = NON_SECURE; 434 435 /* Program EL3 registers to enable entry into the next EL */ 436 if (k32_64 == 0) 437 next_image_info = bl31_plat_get_next_kernel32_ep_info(); 438 else 439 next_image_info = bl31_plat_get_next_kernel64_ep_info(); 440 441 assert(next_image_info); 442 assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr)); 443 444 INFO("BL3-1: Preparing for EL3 exit to %s world, Kernel\n", 445 (image_type == SECURE) ? "secure" : "normal"); 446 INFO("BL3-1: Next image address = 0x%llx\n", 447 (unsigned long long) next_image_info->pc); 448 INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr); 449 cm_init_context(read_mpidr_el1(), next_image_info); 450 cm_prepare_el3_exit(image_type); 451 } 452
