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      1 /*
      2  * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * SPDX-License-Identifier: BSD-3-Clause
      5  */
      6 #include <arch_helpers.h>
      7 #include <arm_gic.h>
      8 #include <bl_common.h>
      9 #include <cci.h>
     10 #include <debug.h>
     11 #include <mt8173_def.h>
     12 #include <platform_def.h>
     13 #include <utils.h>
     14 #include <xlat_tables.h>
     15 
     16 static const int cci_map[] = {
     17 	PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX,
     18 	PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX
     19 };
     20 
     21 /* Table of regions to map using the MMU.  */
     22 const mmap_region_t plat_mmap[] = {
     23 	/* for TF text, RO, RW */
     24 	MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE,
     25 			MT_MEMORY | MT_RW | MT_SECURE),
     26 	MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
     27 			MT_DEVICE | MT_RW | MT_SECURE),
     28 	MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
     29 			MT_DEVICE | MT_RW | MT_SECURE),
     30 	{ 0 }
     31 
     32 };
     33 
     34 /*******************************************************************************
     35  * Macro generating the code for the function setting up the pagetables as per
     36  * the platform memory map & initialize the mmu, for the given exception level
     37  ******************************************************************************/
     38 #define DEFINE_CONFIGURE_MMU_EL(_el)					\
     39 	void plat_configure_mmu_el ## _el(unsigned long total_base,	\
     40 					  unsigned long total_size,	\
     41 					  unsigned long ro_start,	\
     42 					  unsigned long ro_limit,	\
     43 					  unsigned long coh_start,	\
     44 					  unsigned long coh_limit)	\
     45 	{								\
     46 		mmap_add_region(total_base, total_base,			\
     47 				total_size,				\
     48 				MT_MEMORY | MT_RW | MT_SECURE);		\
     49 		mmap_add_region(ro_start, ro_start,			\
     50 				ro_limit - ro_start,			\
     51 				MT_MEMORY | MT_RO | MT_SECURE);		\
     52 		mmap_add_region(coh_start, coh_start,			\
     53 				coh_limit - coh_start,			\
     54 				MT_DEVICE | MT_RW | MT_SECURE);		\
     55 		mmap_add(plat_mmap);					\
     56 		init_xlat_tables();					\
     57 									\
     58 		enable_mmu_el ## _el(0);				\
     59 	}
     60 
     61 /* Define EL3 variants of the function initialising the MMU */
     62 DEFINE_CONFIGURE_MMU_EL(3)
     63 
     64 unsigned int plat_get_syscnt_freq2(void)
     65 {
     66 	return SYS_COUNTER_FREQ_IN_TICKS;
     67 }
     68 
     69 void plat_cci_init(void)
     70 {
     71 	/* Initialize CCI driver */
     72 	cci_init(PLAT_MT_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
     73 }
     74 
     75 void plat_cci_enable(void)
     76 {
     77 	/*
     78 	 * Enable CCI coherency for this cluster.
     79 	 * No need for locks as no other cpu is active at the moment.
     80 	 */
     81 	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
     82 }
     83 
     84 void plat_cci_disable(void)
     85 {
     86 	cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
     87 }
     88