1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <bl_common.h> 8 #include <common_def.h> 9 #include <console.h> 10 #include <debug.h> 11 #include <generic_delay_timer.h> 12 #include <mcucfg.h> 13 #include <mmio.h> 14 #include <mtcmos.h> 15 #include <plat_arm.h> 16 #include <plat_private.h> 17 #include <platform.h> 18 #include <spm.h> 19 20 /******************************************************************************* 21 * Declarations of linker defined symbols which will help us find the layout 22 * of trusted SRAM 23 ******************************************************************************/ 24 unsigned long __RO_START__; 25 unsigned long __RO_END__; 26 27 /* 28 * The next 3 constants identify the extents of the code, RO data region and the 29 * limit of the BL31 image. These addresses are used by the MMU setup code and 30 * therefore they must be page-aligned. It is the responsibility of the linker 31 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 32 * refer to page-aligned addresses. 33 */ 34 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 35 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 36 #define BL31_END (unsigned long)(&__BL31_END__) 37 38 static entry_point_info_t bl32_ep_info; 39 static entry_point_info_t bl33_ep_info; 40 41 static void platform_setup_cpu(void) 42 { 43 /* turn off all the little core's power except cpu 0 */ 44 mtcmos_little_cpu_off(); 45 46 /* setup big cores */ 47 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, 48 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 49 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 50 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 51 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 52 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 53 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); 54 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, 55 MP1_SW_CG_GEN); 56 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, 57 MP1_L2RSTDISABLE); 58 59 /* set big cores arm64 boot mode */ 60 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, 61 MP1_CPUCFG_64BIT); 62 63 /* set LITTLE cores arm64 boot mode */ 64 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, 65 MP0_CPUCFG_64BIT); 66 67 /* enable dcm control */ 68 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, 69 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN | 70 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN | 71 INFRACLK_PSYS_DYNAMIC_CG_EN); 72 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, 73 L2C_SRAM_DCM_EN); 74 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, 75 MCU_BUS_DCM_EN); 76 } 77 78 static void platform_setup_sram(void) 79 { 80 /* protect BL31 memory from non-secure read/write access */ 81 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); 82 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); 83 } 84 85 /******************************************************************************* 86 * Return a pointer to the 'entry_point_info' structure of the next image for 87 * the security state specified. BL33 corresponds to the non-secure image type 88 * while BL32 corresponds to the secure image type. A NULL pointer is returned 89 * if the image does not exist. 90 ******************************************************************************/ 91 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 92 { 93 entry_point_info_t *next_image_info; 94 95 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 96 97 /* None of the images on this platform can have 0x0 as the entrypoint */ 98 if (next_image_info->pc) 99 return next_image_info; 100 else 101 return NULL; 102 } 103 104 /******************************************************************************* 105 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 106 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 107 * are lost (potentially). This needs to be done before the MMU is initialized 108 * so that the memory layout can be used while creating page tables. 109 * BL2 has flushed this information to memory, so we are guaranteed to pick up 110 * good data. 111 ******************************************************************************/ 112 void bl31_early_platform_setup(bl31_params_t *from_bl2, 113 void *plat_params_from_bl2) 114 { 115 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); 116 117 VERBOSE("bl31_setup\n"); 118 119 assert(from_bl2 != NULL); 120 assert(from_bl2->h.type == PARAM_BL31); 121 assert(from_bl2->h.version >= VERSION_1); 122 123 bl32_ep_info = *from_bl2->bl32_ep_info; 124 bl33_ep_info = *from_bl2->bl33_ep_info; 125 } 126 127 /******************************************************************************* 128 * Perform any BL3-1 platform setup code 129 ******************************************************************************/ 130 void bl31_platform_setup(void) 131 { 132 platform_setup_cpu(); 133 platform_setup_sram(); 134 135 generic_delay_timer_init(); 136 137 /* Initialize the gic cpu and distributor interfaces */ 138 plat_arm_gic_driver_init(); 139 plat_arm_gic_init(); 140 141 #if ENABLE_PLAT_COMPAT 142 /* Topologies are best known to the platform. */ 143 mt_setup_topology(); 144 #endif 145 146 /* Initialize spm at boot time */ 147 spm_boot_init(); 148 } 149 150 /******************************************************************************* 151 * Perform the very early platform specific architectural setup here. At the 152 * moment this is only intializes the mmu in a quick and dirty way. 153 ******************************************************************************/ 154 void bl31_plat_arch_setup(void) 155 { 156 plat_cci_init(); 157 plat_cci_enable(); 158 159 plat_configure_mmu_el3(BL31_RO_BASE, 160 BL_COHERENT_RAM_END - BL31_RO_BASE, 161 BL31_RO_BASE, 162 BL31_RO_LIMIT, 163 BL_COHERENT_RAM_BASE, 164 BL_COHERENT_RAM_END); 165 } 166 167
