1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <asm_macros.S> 9 #include <common_def.h> 10 #include <memctrl_v2.h> 11 #include <tegra_def.h> 12 13 #define TEGRA186_SMMU_CTX_SIZE 0x420 14 15 .globl tegra186_cpu_reset_handler 16 17 /* CPU reset handler routine */ 18 func tegra186_cpu_reset_handler _align=4 19 /* 20 * The TZRAM loses state during System Suspend. We use this 21 * information to decide if the reset handler is running after a 22 * System Suspend. Resume from system suspend requires restoring 23 * the entire state from TZDRAM to TZRAM. 24 */ 25 mov x0, #BL31_BASE 26 ldr x0, [x0] 27 cbnz x0, boot_cpu 28 29 /* resume from system suspend */ 30 mov x0, #BL31_BASE 31 adr x1, __tegra186_cpu_reset_handler_end 32 adr x2, __tegra186_cpu_reset_handler_data 33 ldr x2, [x2, #8] 34 35 /* memcpy16 */ 36 m_loop16: 37 cmp x2, #16 38 b.lt m_loop1 39 ldp x3, x4, [x1], #16 40 stp x3, x4, [x0], #16 41 sub x2, x2, #16 42 b m_loop16 43 /* copy byte per byte */ 44 m_loop1: 45 cbz x2, boot_cpu 46 ldrb w3, [x1], #1 47 strb w3, [x0], #1 48 subs x2, x2, #1 49 b.ne m_loop1 50 51 boot_cpu: 52 adr x0, __tegra186_cpu_reset_handler_data 53 ldr x0, [x0] 54 br x0 55 endfunc tegra186_cpu_reset_handler 56 57 /* 58 * Tegra186 reset data (offset 0x0 - 0x430) 59 * 60 * 0x000: secure world's entrypoint 61 * 0x008: BL31 size (RO + RW) 62 * 0x00C: SMMU context start 63 * 0x42C: SMMU context end 64 */ 65 66 .align 4 67 .type __tegra186_cpu_reset_handler_data, %object 68 .globl __tegra186_cpu_reset_handler_data 69 __tegra186_cpu_reset_handler_data: 70 .quad tegra_secure_entrypoint 71 .quad __BL31_END__ - BL31_BASE 72 .globl __tegra186_smmu_context 73 __tegra186_smmu_context: 74 .rept TEGRA186_SMMU_CTX_SIZE 75 .quad 0 76 .endr 77 .size __tegra186_cpu_reset_handler_data, \ 78 . - __tegra186_cpu_reset_handler_data 79 80 .align 4 81 .globl __tegra186_cpu_reset_handler_end 82 __tegra186_cpu_reset_handler_end: 83
