1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <console.h> 9 #include <ddr_parameter.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <mmio.h> 13 #include <plat_private.h> 14 #include <platform_def.h> 15 #include <rk3328_def.h> 16 #include <soc.h> 17 18 /* Table of regions to map using the MMU. */ 19 const mmap_region_t plat_rk_mmap[] = { 20 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE, 21 MT_DEVICE | MT_RW | MT_SECURE), 22 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 23 MT_DEVICE | MT_RW | MT_SECURE), 24 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 25 MT_DEVICE | MT_RW | MT_SECURE), 26 MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE, 27 MT_DEVICE | MT_RW | MT_SECURE), 28 MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE, 29 MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE, 31 MT_DEVICE | MT_RW | MT_SECURE), 32 MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE, 33 MT_DEVICE | MT_RW | MT_SECURE), 34 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, 35 MT_DEVICE | MT_RW | MT_SECURE), 36 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, 37 MT_DEVICE | MT_RW | MT_SECURE), 38 MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE, 39 MT_DEVICE | MT_RW | MT_SECURE), 40 MAP_REGION_FLAT(FIREWALL_CFG_BASE, FIREWALL_CFG_SIZE, 41 MT_DEVICE | MT_RW | MT_SECURE), 42 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 47 MT_MEMORY | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE), 50 MAP_REGION_FLAT(DDR_GRF_BASE, DDR_GRF_SIZE, 51 MT_DEVICE | MT_RW | MT_SECURE), 52 MAP_REGION_FLAT(DDR_UPCTL_BASE, DDR_UPCTL_SIZE, 53 MT_DEVICE | MT_RW | MT_SECURE), 54 MAP_REGION_FLAT(PWM_BASE, PWM_SIZE, 55 MT_DEVICE | MT_RW | MT_SECURE), 56 MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE), 58 MAP_REGION_FLAT(EFUSE8_BASE, EFUSE8_SIZE, 59 MT_DEVICE | MT_RW | MT_SECURE), 60 MAP_REGION_FLAT(EFUSE32_BASE, EFUSE32_SIZE, 61 MT_DEVICE | MT_RW | MT_SECURE), 62 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE, 63 MT_DEVICE | MT_RW | MT_SECURE), 64 MAP_REGION_FLAT(SERVER_MSCH_BASE, SERVER_MSCH_SIZE, 65 MT_DEVICE | MT_RW | MT_SECURE), 66 MAP_REGION_FLAT(DDR_MONITOR_BASE, DDR_MONITOR_SIZE, 67 MT_DEVICE | MT_RW | MT_SECURE), 68 MAP_REGION_FLAT(VOP_BASE, VOP_SIZE, 69 MT_DEVICE | MT_RW | MT_SECURE), 70 71 { 0 } 72 }; 73 74 /* The RockChip power domain tree descriptor */ 75 const unsigned char rockchip_power_domain_tree_desc[] = { 76 /* No of root nodes */ 77 PLATFORM_SYSTEM_COUNT, 78 /* No of children for the root node */ 79 PLATFORM_CLUSTER_COUNT, 80 /* No of children for the first cluster node */ 81 PLATFORM_CLUSTER0_CORE_COUNT, 82 }; 83 84 void secure_timer_init(void) 85 { 86 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT0, 0xffffffff); 87 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT1, 0xffffffff); 88 /* auto reload & enable the timer */ 89 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); 90 } 91 92 void sgrf_init(void) 93 { 94 uint32_t i, val; 95 struct param_ddr_usage usg; 96 97 /* general secure regions */ 98 usg = ddr_region_usage_parse(DDR_PARAM_BASE, 99 PLAT_MAX_DDR_CAPACITY_MB); 100 for (i = 0; i < usg.s_nr; i++) { 101 /* enable secure */ 102 val = mmio_read_32(FIREWALL_DDR_BASE + 103 FIREWALL_DDR_FW_DDR_CON_REG); 104 val |= BIT(7 - i); 105 mmio_write_32(FIREWALL_DDR_BASE + 106 FIREWALL_DDR_FW_DDR_CON_REG, val); 107 /* map top and base */ 108 mmio_write_32(FIREWALL_DDR_BASE + 109 FIREWALL_DDR_FW_DDR_RGN(7 - i), 110 RG_MAP_SECURE(usg.s_top[i], usg.s_base[i])); 111 } 112 113 /* set ddr rgn0_top and rga0_top as 0 */ 114 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); 115 116 /* set all slave ip into no-secure, except stimer */ 117 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(0), 118 SGRF_SLV_S_ALL_NS); 119 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(1), 120 SGRF_SLV_S_ALL_NS); 121 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(2), 122 SGRF_SLV_S_ALL_NS | STIMER_S); 123 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(3), 124 SGRF_SLV_S_ALL_NS); 125 126 /* set all master ip into no-secure */ 127 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), 0xf0000000); 128 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_MST_S_ALL_NS); 129 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_MST_S_ALL_NS); 130 131 /* set DMAC into no-secure */ 132 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_IRQ_BOOT_NS); 133 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(4), DMA_PERI_CH_NS_15_0); 134 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_PERI_CH_NS_19_16); 135 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_MANAGER_BOOT_NS); 136 137 /* soft reset dma before use */ 138 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ); 139 udelay(5); 140 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS); 141 } 142 143 void plat_rockchip_soc_init(void) 144 { 145 secure_timer_init(); 146 sgrf_init(); 147 148 NOTICE("BL31:Rockchip release version: v%d.%d\n", 149 MAJOR_VERSION, MINOR_VERSION); 150 } 151
