1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <dram_regs.h> 8 #include <m0_param.h> 9 #include <pmu_bits.h> 10 #include <pmu_regs.h> 11 #include "misc_regs.h" 12 #include "rk3399_mcu.h" 13 14 static uint32_t gatedis_con0; 15 16 static void idle_port(void) 17 { 18 gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); 19 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); 20 21 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 22 (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); 23 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 24 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) != 25 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) 26 continue; 27 } 28 29 static void deidle_port(void) 30 { 31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, 32 (1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1)); 33 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & 34 ((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) 35 continue; 36 37 /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ 38 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); 39 } 40 41 static void ddr_set_pll(void) 42 { 43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); 44 45 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); 46 mmio_write_32(CRU_BASE + CRU_DPLL_CON0, 47 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); 48 mmio_write_32(CRU_BASE + CRU_DPLL_CON1, 49 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); 50 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); 51 52 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) 53 continue; 54 55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); 56 } 57 58 void handle_dram(void) 59 { 60 mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); 61 mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); 62 idle_port(); 63 64 mmio_write_32(CIC_BASE + CIC_CTRL0, 65 (((0x3 << 4) | (1 << 2) | 1) << 16) | 66 (1 << 2) | 1 | 67 mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); 68 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) 69 continue; 70 71 ddr_set_pll(); 72 mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002); 73 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) 74 continue; 75 76 deidle_port(); 77 mmio_clrbits_32(PHY_REG(0, 927), (1 << 22)); 78 mmio_clrbits_32(PHY_REG(1, 927), (1 << 22)); 79 } 80
