1 #/** @file 2 # ARM processor package. 3 # 4 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> 5 # Copyright (c) 2011 - 2015, ARM Limited. All rights reserved. 6 # 7 # This program and the accompanying materials 8 # are licensed and made available under the terms and conditions of the BSD License 9 # which accompanies this distribution. The full text of the license may be found at 10 # http://opensource.org/licenses/bsd-license.php 11 # 12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14 # 15 #**/ 16 17 [Defines] 18 DEC_SPECIFICATION = 0x00010005 19 PACKAGE_NAME = ArmPkg 20 PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F 21 PACKAGE_VERSION = 0.1 22 23 ################################################################################ 24 # 25 # Include Section - list of Include Paths that are provided by this package. 26 # Comments are used for Keywords and Module Types. 27 # 28 # Supported Module Types: 29 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION 30 # 31 ################################################################################ 32 [Includes.common] 33 Include # Root include for the package 34 35 [LibraryClasses.common] 36 ArmLib|Include/Library/ArmLib.h 37 ArmMmuLib|Include/Library/ArmMmuLib.h 38 SemihostLib|Include/Library/Semihosting.h 39 UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h 40 DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h 41 ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h 42 ArmGicArchLib|Include/Library/ArmGicArchLib.h 43 44 [Guids.common] 45 gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } } 46 47 ## ARM MPCore table 48 # Include/Guid/ArmMpCoreInfo.h 49 gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} } 50 51 [Ppis] 52 ## Include/Ppi/ArmMpCoreInfo.h 53 gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} } 54 55 [Protocols.common] 56 gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } } 57 58 [PcdsFeatureFlag.common] 59 gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001 60 61 # On ARM Architecture with the Security Extension, the address for the 62 # Vector Table can be mapped anywhere in the memory map. It means we can 63 # point the Exception Vector Table to its location in CpuDxe. 64 # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress) 65 gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022 66 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before 67 # it has been configured by the CPU DXE 68 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032 69 70 # Define if the spin-table mechanism is used by the secondary cores when booting 71 # Linux (instead of PSCI) 72 gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033 73 74 # Define if the GICv3 controller should use the GICv2 legacy 75 gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 76 77 [PcdsFeatureFlag.ARM] 78 # Whether to map normal memory as non-shareable. FALSE is the safe choice, but 79 # TRUE may be appropriate to fix performance problems if you don't care about 80 # hardware coherency (i.e., no virtualization or cache coherent DMA) 81 gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043 82 83 [PcdsFixedAtBuild.common] 84 gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006 85 86 # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file. 87 # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. 88 gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024 89 90 gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002 91 # This PCD will free the unallocated buffers if their size reach this threshold. 92 # We set the default value to 512MB. 93 gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003 94 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004 95 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005 96 97 # 98 # ARM Secure Firmware PCDs 99 # 100 gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015 101 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016 102 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F 103 gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030 104 105 # 106 # ARM Hypervisor Firmware PCDs 107 # 108 gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A 109 gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B 110 gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C 111 gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D 112 113 # Use ClusterId + CoreId to identify the PrimaryCore 114 gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031 115 # The Primary Core is ClusterId[0] & CoreId[0] 116 gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037 117 118 # 119 # ARM L2x0 PCDs 120 # 121 gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B 122 123 # 124 # BdsLib 125 # 126 # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory 127 gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F 128 # Maximum file size for TFTP servers that do not support 'tsize' extension 129 gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000 130 131 # 132 # ARM Normal (or Non Secure) Firmware PCDs 133 # 134 gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C 135 gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E 136 137 # 138 # Value to add to a host address to obtain a device address, using 139 # unsigned 64-bit integer arithmetic on both ARM and AArch64. This 140 # means we can rely on truncation on overflow to specify negative 141 # offsets. 142 # 143 gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044 144 145 [PcdsFixedAtBuild.common, PcdsPatchableInModule.common] 146 gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B 147 gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D 148 149 [PcdsFixedAtBuild.ARM] 150 # 151 # ARM Security Extension 152 # 153 154 # Secure Configuration Register 155 # - BIT0 : NS - Non Secure bit 156 # - BIT1 : IRQ Handler 157 # - BIT2 : FIQ Handler 158 # - BIT3 : EA - External Abort 159 # - BIT4 : FW - F bit writable 160 # - BIT5 : AW - A bit writable 161 # - BIT6 : nET - Not Early Termination 162 # - BIT7 : SCD - Secure Monitor Call Disable 163 # - BIT8 : HCE - Hyp Call enable 164 # - BIT9 : SIF - Secure Instruction Fetch 165 # 0x31 = NS | EA | FW 166 gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038 167 168 # By default we do not do a transition to non-secure mode 169 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E 170 171 # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory 172 gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020 173 174 # If the fixed FDT address is not available, then it should be loaded below the kernel. 175 # The recommendation from the Linux kernel is to have the FDT below 16KB. 176 # (see the kernel doc: Documentation/arm/Booting) 177 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023 178 # The FDT blob must be loaded at a 64bit aligned address. 179 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026 180 181 # Non Secure Access Control Register 182 # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality 183 # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 184 # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable 185 # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable 186 # 0xC00 = cp10 | cp11 187 gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039 188 189 [PcdsFixedAtBuild.AARCH64] 190 # 191 # AArch64 Security Extension 192 # 193 194 # Secure Configuration Register 195 # - BIT0 : NS - Non Secure bit 196 # - BIT1 : IRQ Handler 197 # - BIT2 : FIQ Handler 198 # - BIT3 : EA - External Abort 199 # - BIT4 : FW - F bit writable 200 # - BIT5 : AW - A bit writable 201 # - BIT6 : nET - Not Early Termination 202 # - BIT7 : SCD - Secure Monitor Call Disable 203 # - BIT8 : HCE - Hyp Call enable 204 # - BIT9 : SIF - Secure Instruction Fetch 205 # - BIT10: RW - Register width control for lower exception levels 206 # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer 207 # - BIT12: TWI - Trap WFI 208 # - BIT13: TWE - Trap WFE 209 # 0x501 = NS | HCE | RW 210 gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038 211 212 # By default we do transition to EL2 non-secure mode with Stack for EL2. 213 # Mode Description Bits 214 # NS EL2 SP2 all interrupts disabled = 0x3c9 215 # NS EL1 SP1 all interrupts disabled = 0x3c5 216 # Other modes include using SP0 or switching to Aarch32, but these are 217 # not currently supported. 218 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E 219 # If the fixed FDT address is not available, then it should be loaded above the kernel. 220 # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB. 221 # (see the kernel doc: Documentation/arm64/booting.txt) 222 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023 223 # The FDT blob must be loaded at a 2MB aligned address. 224 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026 225 226 227 # 228 # These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be 229 # redefined when using UEFI in a context of virtual machine. 230 # 231 [PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common] 232 233 # System Memory (DRAM): These PCDs define the region of in-built system memory 234 # Some platforms can get DRAM extensions, these additional regions will be declared 235 # to UEFI by ArmPlatformLib 236 gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029 237 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A 238 239 [PcdsFixedAtBuild.common, PcdsDynamic.common] 240 # 241 # ARM Architectural Timer 242 # 243 gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034 244 245 # ARM Architectural Timer Interrupt(GIC PPI) numbers 246 gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 247 gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036 248 gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040 249 gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041 250 251 # 252 # ARM Generic Watchdog 253 # 254 255 gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007 256 gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008 257 gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009 258 259 # 260 # ARM Generic Interrupt Controller 261 # 262 gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C 263 # Base address for the GIC Redistributor region that contains the boot CPU 264 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E 265 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D 266 gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 267 268 # 269 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively. 270 # Note that "IO" is just another MMIO range that simulates IO space; there 271 # are no special instructions to access it. 272 # 273 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are 274 # specific to their containing address spaces. In order to get the physical 275 # address for the CPU, for a given access, the respective translation value 276 # has to be added. 277 # 278 # The translations always have to be initialized like this, using UINT64: 279 # 280 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space 281 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space 282 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space 283 # 284 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase; 285 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base; 286 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base; 287 # 288 # because (a) the target address space (ie. the cpu-physical space) is 289 # 64-bit, and (b) the translation values are meant as offsets for *modular* 290 # arithmetic. 291 # 292 # Accordingly, the translation itself needs to be implemented as: 293 # 294 # UINT64 UntranslatedIoAddress; // input parameter 295 # UINT32 UntranslatedMmio32Address; // input parameter 296 # UINT64 UntranslatedMmio64Address; // input parameter 297 # 298 # UINT64 TranslatedIoAddress; // output parameter 299 # UINT64 TranslatedMmio32Address; // output parameter 300 # UINT64 TranslatedMmio64Address; // output parameter 301 # 302 # TranslatedIoAddress = UntranslatedIoAddress + 303 # PcdPciIoTranslation; 304 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address + 305 # PcdPciMmio32Translation; 306 # TranslatedMmio64Address = UntranslatedMmio64Address + 307 # PcdPciMmio64Translation; 308 # 309 # The modular arithmetic performed in UINT64 ensures that the translation 310 # works correctly regardless of the relation between IoCpuBase and 311 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and 312 # PcdPciMmio64Base. 313 # 314 gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050 315 gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051 316 gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052 317 gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053 318 gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054 319 gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055 320 gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056 321 gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057 322 gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058 323 324 # 325 # Inclusive range of allowed PCI buses. 326 # 327 gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059 328 gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A 329
