1 /** @file HDLcd.h 2 3 Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR> 4 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #ifndef _HDLCD_H_ 16 #define _HDLCD_H_ 17 18 // 19 // HDLCD Controller Register Offsets 20 // 21 22 #define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000) 23 #define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010) 24 #define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014) 25 #define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018) 26 #define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C) 27 #define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100) 28 #define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104) 29 #define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108) 30 #define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C) 31 #define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110) 32 #define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200) 33 #define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204) 34 #define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208) 35 #define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C) 36 #define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210) 37 #define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214) 38 #define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218) 39 #define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C) 40 #define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220) 41 #define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230) 42 #define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240) 43 #define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244) 44 #define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248) 45 #define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C) 46 47 48 // 49 // HDLCD Values of registers 50 // 51 52 // HDLCD Interrupt mask, clear and status register 53 #define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */ 54 #define HDLCD_BUS_ERROR BIT1 /* DMA bus error */ 55 #define HDLCD_SYNC BIT2 /* Vertical sync */ 56 #define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */ 57 58 // CLCD_CONTROL Control register 59 #define HDLCD_DISABLE 0 60 #define HDLCD_ENABLE BIT0 61 62 // Bus Options 63 #define HDLCD_BURST_1 BIT0 64 #define HDLCD_BURST_2 BIT1 65 #define HDLCD_BURST_4 BIT2 66 #define HDLCD_BURST_8 BIT3 67 #define HDLCD_BURST_16 BIT4 68 69 // Polarities - HIGH 70 #define HDLCD_VSYNC_HIGH BIT0 71 #define HDLCD_HSYNC_HIGH BIT1 72 #define HDLCD_DATEN_HIGH BIT2 73 #define HDLCD_DATA_HIGH BIT3 74 #define HDLCD_PXCLK_HIGH BIT4 75 // Polarities - LOW (for completion and for ease of understanding the hardware settings) 76 #define HDLCD_VSYNC_LOW 0 77 #define HDLCD_HSYNC_LOW 0 78 #define HDLCD_DATEN_LOW 0 79 #define HDLCD_DATA_LOW 0 80 #define HDLCD_PXCLK_LOW 0 81 82 // Pixel Format 83 #define HDLCD_LITTLE_ENDIAN (0 << 31) 84 #define HDLCD_BIG_ENDIAN (1 << 31) 85 86 // Number of bytes per pixel 87 #define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) 88 89 #endif /* _HDLCD_H_ */ 90
