1 /** @file 2 3 This file contains the definination for host controller register operation routines. 4 5 Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR> 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef _EFI_EHCI_REG_H_ 17 #define _EFI_EHCI_REG_H_ 18 19 // 20 // EHCI register offset 21 // 22 23 24 // 25 // Capability register offset 26 // 27 #define EHC_CAPLENGTH_OFFSET 0 // Capability register length offset 28 #define EHC_HCSPARAMS_OFFSET 0x04 // Structural Parameters 04-07h 29 #define EHC_HCCPARAMS_OFFSET 0x08 // Capability parameters offset 30 31 // 32 // Capability register bit definition 33 // 34 #define HCSP_NPORTS 0x0F // Number of root hub port 35 #define HCSP_PPC 0x10 // Port Power Control 36 #define HCCP_64BIT 0x01 // 64-bit addressing capability 37 38 // 39 // Operational register offset 40 // 41 #define EHC_USBCMD_OFFSET 0x0 // USB command register offset 42 #define EHC_USBSTS_OFFSET 0x04 // Statue register offset 43 #define EHC_USBINTR_OFFSET 0x08 // USB interrutp offset 44 #define EHC_FRINDEX_OFFSET 0x0C // Frame index offset 45 #define EHC_CTRLDSSEG_OFFSET 0x10 // Control data structure segment offset 46 #define EHC_FRAME_BASE_OFFSET 0x14 // Frame list base address offset 47 #define EHC_ASYNC_HEAD_OFFSET 0x18 // Next asynchronous list address offset 48 #define EHC_CONFIG_FLAG_OFFSET 0x40 // Configure flag register offset 49 #define EHC_PORT_STAT_OFFSET 0x44 // Port status/control offset 50 51 #define EHC_FRAME_LEN 1024 52 53 // 54 // Register bit definition 55 // 56 #define CONFIGFLAG_ROUTE_EHC 0x01 // Route port to EHC 57 58 #define USBCMD_RUN 0x01 // Run/stop 59 #define USBCMD_RESET 0x02 // Start the host controller reset 60 #define USBCMD_ENABLE_PERIOD 0x10 // Enable periodic schedule 61 #define USBCMD_ENABLE_ASYNC 0x20 // Enable asynchronous schedule 62 #define USBCMD_IAAD 0x40 // Interrupt on async advance doorbell 63 64 #define USBSTS_IAA 0x20 // Interrupt on async advance 65 #define USBSTS_PERIOD_ENABLED 0x4000 // Periodic schedule status 66 #define USBSTS_ASYNC_ENABLED 0x8000 // Asynchronous schedule status 67 #define USBSTS_HALT 0x1000 // Host controller halted 68 #define USBSTS_SYS_ERROR 0x10 // Host system error 69 #define USBSTS_INTACK_MASK 0x003F // Mask for the interrupt ACK, the WC 70 // (write clean) bits in USBSTS register 71 72 #define PORTSC_CONN 0x01 // Current Connect Status 73 #define PORTSC_CONN_CHANGE 0x02 // Connect Status Change 74 #define PORTSC_ENABLED 0x04 // Port Enable / Disable 75 #define PORTSC_ENABLE_CHANGE 0x08 // Port Enable / Disable Change 76 #define PORTSC_OVERCUR 0x10 // Over current Active 77 #define PORTSC_OVERCUR_CHANGE 0x20 // Over current Change 78 #define PORSTSC_RESUME 0x40 // Force Port Resume 79 #define PORTSC_SUSPEND 0x80 // Port Suspend State 80 #define PORTSC_RESET 0x100 // Port Reset 81 #define PORTSC_LINESTATE_K 0x400 // Line Status K-state 82 #define PORTSC_LINESTATE_J 0x800 // Line Status J-state 83 #define PORTSC_POWER 0x1000 // Port Power 84 #define PORTSC_OWNER 0x2000 // Port Owner 85 #define PORTSC_CHANGE_MASK 0x2A // Mask of the port change bits, 86 // they are WC (write clean) 87 // 88 // PCI Configuration Registers 89 // 90 #define EHC_BAR_INDEX 0 // how many bytes away from USB_BASE to 0x10 91 92 // 93 // Debug port capability id 94 // 95 #define EHC_DEBUG_PORT_CAP_ID 0x0A 96 97 #define EHC_LINK_TERMINATED(Link) (((Link) & 0x01) != 0) 98 99 #define EHC_ADDR(High, QhHw32) \ 100 ((VOID *) (UINTN) (LShiftU64 ((High), 32) | ((QhHw32) & 0xFFFFFFF0))) 101 102 #define EHCI_IS_DATAIN(EndpointAddr) EHC_BIT_IS_SET((EndpointAddr), 0x80) 103 104 // 105 // Structure to map the hardware port states to the 106 // UEFI's port states. 107 // 108 typedef struct { 109 UINT16 HwState; 110 UINT16 UefiState; 111 } USB_PORT_STATE_MAP; 112 113 // 114 // Ehci Data and Ctrl Structures 115 // 116 #pragma pack(1) 117 typedef struct { 118 UINT8 ProgInterface; 119 UINT8 SubClassCode; 120 UINT8 BaseCode; 121 } USB_CLASSC; 122 #pragma pack() 123 124 /** 125 Read EHCI capability register. 126 127 @param Ehc The EHCI device. 128 @param Offset Capability register address. 129 130 @return The register content. 131 132 **/ 133 UINT32 134 EhcReadCapRegister ( 135 IN USB2_HC_DEV *Ehc, 136 IN UINT32 Offset 137 ); 138 139 /** 140 Read EHCI debug port register. 141 142 @param Ehc The EHCI device. 143 @param Offset Debug port register address. 144 145 @return The register content read. 146 @retval If err, return 0xffff. 147 148 **/ 149 UINT32 150 EhcReadDbgRegister ( 151 IN USB2_HC_DEV *Ehc, 152 IN UINT32 Offset 153 ); 154 155 /** 156 Read EHCI Operation register. 157 158 @param Ehc The EHCI device. 159 @param Offset The operation register offset. 160 161 @return The register content. 162 163 **/ 164 UINT32 165 EhcReadOpReg ( 166 IN USB2_HC_DEV *Ehc, 167 IN UINT32 Offset 168 ); 169 170 171 /** 172 Write the data to the EHCI operation register. 173 174 @param Ehc The EHCI device. 175 @param Offset EHCI operation register offset. 176 @param Data The data to write. 177 178 **/ 179 VOID 180 EhcWriteOpReg ( 181 IN USB2_HC_DEV *Ehc, 182 IN UINT32 Offset, 183 IN UINT32 Data 184 ); 185 186 /** 187 Set one bit of the operational register while keeping other bits. 188 189 @param Ehc The EHCI device. 190 @param Offset The offset of the operational register. 191 @param Bit The bit mask of the register to set. 192 193 **/ 194 VOID 195 EhcSetOpRegBit ( 196 IN USB2_HC_DEV *Ehc, 197 IN UINT32 Offset, 198 IN UINT32 Bit 199 ); 200 201 /** 202 Clear one bit of the operational register while keeping other bits. 203 204 @param Ehc The EHCI device. 205 @param Offset The offset of the operational register. 206 @param Bit The bit mask of the register to clear. 207 208 **/ 209 VOID 210 EhcClearOpRegBit ( 211 IN USB2_HC_DEV *Ehc, 212 IN UINT32 Offset, 213 IN UINT32 Bit 214 ); 215 216 /** 217 Add support for UEFI Over Legacy (UoL) feature, stop 218 the legacy USB SMI support. 219 220 @param Ehc The EHCI device. 221 222 **/ 223 VOID 224 EhcClearLegacySupport ( 225 IN USB2_HC_DEV *Ehc 226 ); 227 228 229 230 /** 231 Set door bell and wait it to be ACKed by host controller. 232 This function is used to synchronize with the hardware. 233 234 @param Ehc The EHCI device. 235 @param Timeout The time to wait before abort (in millisecond, ms). 236 237 @retval EFI_SUCCESS Synchronized with the hardware. 238 @retval EFI_TIMEOUT Time out happened while waiting door bell to set. 239 240 **/ 241 EFI_STATUS 242 EhcSetAndWaitDoorBell ( 243 IN USB2_HC_DEV *Ehc, 244 IN UINT32 Timeout 245 ); 246 247 248 /** 249 Clear all the interrutp status bits, these bits are Write-Clean. 250 251 @param Ehc The EHCI device. 252 253 **/ 254 VOID 255 EhcAckAllInterrupt ( 256 IN USB2_HC_DEV *Ehc 257 ); 258 259 260 261 /** 262 Whether Ehc is halted. 263 264 @param Ehc The EHCI device. 265 266 @retval TRUE The controller is halted. 267 @retval FALSE It isn't halted. 268 269 **/ 270 BOOLEAN 271 EhcIsHalt ( 272 IN USB2_HC_DEV *Ehc 273 ); 274 275 276 /** 277 Whether system error occurred. 278 279 @param Ehc The EHCI device. 280 281 @retval TRUE System error happened. 282 @retval FALSE No system error. 283 284 **/ 285 BOOLEAN 286 EhcIsSysError ( 287 IN USB2_HC_DEV *Ehc 288 ); 289 290 291 /** 292 Reset the host controller. 293 294 @param Ehc The EHCI device. 295 @param Timeout Time to wait before abort (in millisecond, ms). 296 297 @retval EFI_SUCCESS The host controller is reset. 298 @return Others Failed to reset the host. 299 300 **/ 301 EFI_STATUS 302 EhcResetHC ( 303 IN USB2_HC_DEV *Ehc, 304 IN UINT32 Timeout 305 ); 306 307 308 /** 309 Halt the host controller. 310 311 @param Ehc The EHCI device. 312 @param Timeout Time to wait before abort. 313 314 @return EFI_SUCCESS The EHCI is halt. 315 @return EFI_TIMEOUT Failed to halt the controller before Timeout. 316 317 **/ 318 EFI_STATUS 319 EhcHaltHC ( 320 IN USB2_HC_DEV *Ehc, 321 IN UINT32 Timeout 322 ); 323 324 325 /** 326 Set the EHCI to run. 327 328 @param Ehc The EHCI device. 329 @param Timeout Time to wait before abort. 330 331 @return EFI_SUCCESS The EHCI is running. 332 @return Others Failed to set the EHCI to run. 333 334 **/ 335 EFI_STATUS 336 EhcRunHC ( 337 IN USB2_HC_DEV *Ehc, 338 IN UINT32 Timeout 339 ); 340 341 342 343 /** 344 Initialize the HC hardware. 345 EHCI spec lists the five things to do to initialize the hardware: 346 1. Program CTRLDSSEGMENT 347 2. Set USBINTR to enable interrupts 348 3. Set periodic list base 349 4. Set USBCMD, interrupt threshold, frame list size etc 350 5. Write 1 to CONFIGFLAG to route all ports to EHCI 351 352 @param Ehc The EHCI device. 353 354 @return EFI_SUCCESS The EHCI has come out of halt state. 355 @return EFI_TIMEOUT Time out happened. 356 357 **/ 358 EFI_STATUS 359 EhcInitHC ( 360 IN USB2_HC_DEV *Ehc 361 ); 362 363 #endif 364
