1 /** @file 2 Provides services to access PCI Configuration Space using the MMIO PCI Express window. 3 4 This library is identical to the PCI Library, except the access method for performing PCI 5 configuration cycles must be through the 256 MB PCI Express MMIO window whose base address 6 is defined by PcdPciExpressBaseAddress. 7 8 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR> 9 This program and the accompanying materials 10 are licensed and made available under the terms and conditions of the BSD License 11 which accompanies this distribution. The full text of the license may be found at 12 http://opensource.org/licenses/bsd-license.php 13 14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 16 17 **/ 18 19 #ifndef __PCI_EXPRESS_LIB_H__ 20 #define __PCI_EXPRESS_LIB_H__ 21 22 /** 23 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an 24 address that can be passed to the PCI Library functions. 25 26 Computes an address that is compatible with the PCI Library functions. The 27 unused upper bits of Bus, Device, Function and Register are stripped prior to 28 the generation of the address. 29 30 @param Bus PCI Bus number. Range 0..255. 31 @param Device PCI Device number. Range 0..31. 32 @param Function PCI Function number. Range 0..7. 33 @param Register PCI Register number. Range 0..4095. 34 35 @return The encode PCI address. 36 37 **/ 38 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \ 39 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) 40 41 /** 42 Registers a PCI device so PCI configuration registers may be accessed after 43 SetVirtualAddressMap(). 44 45 Registers the PCI device specified by Address so all the PCI configuration 46 registers associated with that PCI device may be accessed after SetVirtualAddressMap() 47 is called. 48 49 If Address > 0x0FFFFFFF, then ASSERT(). 50 51 @param Address Address that encodes the PCI Bus, Device, Function and 52 Register. 53 54 @retval RETURN_SUCCESS The PCI device was registered for runtime access. 55 @retval RETURN_UNSUPPORTED An attempt was made to call this function 56 after ExitBootServices(). 57 @retval RETURN_UNSUPPORTED The resources required to access the PCI device 58 at runtime could not be mapped. 59 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to 60 complete the registration. 61 62 **/ 63 RETURN_STATUS 64 EFIAPI 65 PciExpressRegisterForRuntimeAccess ( 66 IN UINTN Address 67 ); 68 69 /** 70 Reads an 8-bit PCI configuration register. 71 72 Reads and returns the 8-bit PCI configuration register specified by Address. 73 This function must guarantee that all PCI read and write operations are 74 serialized. 75 76 If Address > 0x0FFFFFFF, then ASSERT(). 77 78 @param Address Address that encodes the PCI Bus, Device, Function and 79 Register. 80 81 @return The read value from the PCI configuration register. 82 83 **/ 84 UINT8 85 EFIAPI 86 PciExpressRead8 ( 87 IN UINTN Address 88 ); 89 90 /** 91 Writes an 8-bit PCI configuration register. 92 93 Writes the 8-bit PCI configuration register specified by Address with the 94 value specified by Value. Value is returned. This function must guarantee 95 that all PCI read and write operations are serialized. 96 97 If Address > 0x0FFFFFFF, then ASSERT(). 98 99 @param Address Address that encodes the PCI Bus, Device, Function and 100 Register. 101 @param Value The value to write. 102 103 @return The value written to the PCI configuration register. 104 105 **/ 106 UINT8 107 EFIAPI 108 PciExpressWrite8 ( 109 IN UINTN Address, 110 IN UINT8 Value 111 ); 112 113 /** 114 Performs a bitwise OR of an 8-bit PCI configuration register with 115 an 8-bit value. 116 117 Reads the 8-bit PCI configuration register specified by Address, performs a 118 bitwise OR between the read result and the value specified by 119 OrData, and writes the result to the 8-bit PCI configuration register 120 specified by Address. The value written to the PCI configuration register is 121 returned. This function must guarantee that all PCI read and write operations 122 are serialized. 123 124 If Address > 0x0FFFFFFF, then ASSERT(). 125 126 @param Address Address that encodes the PCI Bus, Device, Function and 127 Register. 128 @param OrData The value to OR with the PCI configuration register. 129 130 @return The value written back to the PCI configuration register. 131 132 **/ 133 UINT8 134 EFIAPI 135 PciExpressOr8 ( 136 IN UINTN Address, 137 IN UINT8 OrData 138 ); 139 140 /** 141 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 142 value. 143 144 Reads the 8-bit PCI configuration register specified by Address, performs a 145 bitwise AND between the read result and the value specified by AndData, and 146 writes the result to the 8-bit PCI configuration register specified by 147 Address. The value written to the PCI configuration register is returned. 148 This function must guarantee that all PCI read and write operations are 149 serialized. 150 151 If Address > 0x0FFFFFFF, then ASSERT(). 152 153 @param Address Address that encodes the PCI Bus, Device, Function and 154 Register. 155 @param AndData The value to AND with the PCI configuration register. 156 157 @return The value written back to the PCI configuration register. 158 159 **/ 160 UINT8 161 EFIAPI 162 PciExpressAnd8 ( 163 IN UINTN Address, 164 IN UINT8 AndData 165 ); 166 167 /** 168 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 169 value, followed a bitwise OR with another 8-bit value. 170 171 Reads the 8-bit PCI configuration register specified by Address, performs a 172 bitwise AND between the read result and the value specified by AndData, 173 performs a bitwise OR between the result of the AND operation and 174 the value specified by OrData, and writes the result to the 8-bit PCI 175 configuration register specified by Address. The value written to the PCI 176 configuration register is returned. This function must guarantee that all PCI 177 read and write operations are serialized. 178 179 If Address > 0x0FFFFFFF, then ASSERT(). 180 181 @param Address Address that encodes the PCI Bus, Device, Function and 182 Register. 183 @param AndData The value to AND with the PCI configuration register. 184 @param OrData The value to OR with the result of the AND operation. 185 186 @return The value written back to the PCI configuration register. 187 188 **/ 189 UINT8 190 EFIAPI 191 PciExpressAndThenOr8 ( 192 IN UINTN Address, 193 IN UINT8 AndData, 194 IN UINT8 OrData 195 ); 196 197 /** 198 Reads a bit field of a PCI configuration register. 199 200 Reads the bit field in an 8-bit PCI configuration register. The bit field is 201 specified by the StartBit and the EndBit. The value of the bit field is 202 returned. 203 204 If Address > 0x0FFFFFFF, then ASSERT(). 205 If StartBit is greater than 7, then ASSERT(). 206 If EndBit is greater than 7, then ASSERT(). 207 If EndBit is less than StartBit, then ASSERT(). 208 209 @param Address PCI configuration register to read. 210 @param StartBit The ordinal of the least significant bit in the bit field. 211 Range 0..7. 212 @param EndBit The ordinal of the most significant bit in the bit field. 213 Range 0..7. 214 215 @return The value of the bit field read from the PCI configuration register. 216 217 **/ 218 UINT8 219 EFIAPI 220 PciExpressBitFieldRead8 ( 221 IN UINTN Address, 222 IN UINTN StartBit, 223 IN UINTN EndBit 224 ); 225 226 /** 227 Writes a bit field to a PCI configuration register. 228 229 Writes Value to the bit field of the PCI configuration register. The bit 230 field is specified by the StartBit and the EndBit. All other bits in the 231 destination PCI configuration register are preserved. The new value of the 232 8-bit register is returned. 233 234 If Address > 0x0FFFFFFF, then ASSERT(). 235 If StartBit is greater than 7, then ASSERT(). 236 If EndBit is greater than 7, then ASSERT(). 237 If EndBit is less than StartBit, then ASSERT(). 238 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 239 240 @param Address PCI configuration register to write. 241 @param StartBit The ordinal of the least significant bit in the bit field. 242 Range 0..7. 243 @param EndBit The ordinal of the most significant bit in the bit field. 244 Range 0..7. 245 @param Value New value of the bit field. 246 247 @return The value written back to the PCI configuration register. 248 249 **/ 250 UINT8 251 EFIAPI 252 PciExpressBitFieldWrite8 ( 253 IN UINTN Address, 254 IN UINTN StartBit, 255 IN UINTN EndBit, 256 IN UINT8 Value 257 ); 258 259 /** 260 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and 261 writes the result back to the bit field in the 8-bit port. 262 263 Reads the 8-bit PCI configuration register specified by Address, performs a 264 bitwise OR between the read result and the value specified by 265 OrData, and writes the result to the 8-bit PCI configuration register 266 specified by Address. The value written to the PCI configuration register is 267 returned. This function must guarantee that all PCI read and write operations 268 are serialized. Extra left bits in OrData are stripped. 269 270 If Address > 0x0FFFFFFF, then ASSERT(). 271 If StartBit is greater than 7, then ASSERT(). 272 If EndBit is greater than 7, then ASSERT(). 273 If EndBit is less than StartBit, then ASSERT(). 274 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 275 276 @param Address PCI configuration register to write. 277 @param StartBit The ordinal of the least significant bit in the bit field. 278 Range 0..7. 279 @param EndBit The ordinal of the most significant bit in the bit field. 280 Range 0..7. 281 @param OrData The value to OR with the PCI configuration register. 282 283 @return The value written back to the PCI configuration register. 284 285 **/ 286 UINT8 287 EFIAPI 288 PciExpressBitFieldOr8 ( 289 IN UINTN Address, 290 IN UINTN StartBit, 291 IN UINTN EndBit, 292 IN UINT8 OrData 293 ); 294 295 /** 296 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise 297 AND, and writes the result back to the bit field in the 8-bit register. 298 299 Reads the 8-bit PCI configuration register specified by Address, performs a 300 bitwise AND between the read result and the value specified by AndData, and 301 writes the result to the 8-bit PCI configuration register specified by 302 Address. The value written to the PCI configuration register is returned. 303 This function must guarantee that all PCI read and write operations are 304 serialized. Extra left bits in AndData are stripped. 305 306 If Address > 0x0FFFFFFF, then ASSERT(). 307 If StartBit is greater than 7, then ASSERT(). 308 If EndBit is greater than 7, then ASSERT(). 309 If EndBit is less than StartBit, then ASSERT(). 310 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 311 312 @param Address PCI configuration register to write. 313 @param StartBit The ordinal of the least significant bit in the bit field. 314 Range 0..7. 315 @param EndBit The ordinal of the most significant bit in the bit field. 316 Range 0..7. 317 @param AndData The value to AND with the PCI configuration register. 318 319 @return The value written back to the PCI configuration register. 320 321 **/ 322 UINT8 323 EFIAPI 324 PciExpressBitFieldAnd8 ( 325 IN UINTN Address, 326 IN UINTN StartBit, 327 IN UINTN EndBit, 328 IN UINT8 AndData 329 ); 330 331 /** 332 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a 333 bitwise OR, and writes the result back to the bit field in the 334 8-bit port. 335 336 Reads the 8-bit PCI configuration register specified by Address, performs a 337 bitwise AND followed by a bitwise OR between the read result and 338 the value specified by AndData, and writes the result to the 8-bit PCI 339 configuration register specified by Address. The value written to the PCI 340 configuration register is returned. This function must guarantee that all PCI 341 read and write operations are serialized. Extra left bits in both AndData and 342 OrData are stripped. 343 344 If Address > 0x0FFFFFFF, then ASSERT(). 345 If StartBit is greater than 7, then ASSERT(). 346 If EndBit is greater than 7, then ASSERT(). 347 If EndBit is less than StartBit, then ASSERT(). 348 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 349 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 350 351 @param Address PCI configuration register to write. 352 @param StartBit The ordinal of the least significant bit in the bit field. 353 Range 0..7. 354 @param EndBit The ordinal of the most significant bit in the bit field. 355 Range 0..7. 356 @param AndData The value to AND with the PCI configuration register. 357 @param OrData The value to OR with the result of the AND operation. 358 359 @return The value written back to the PCI configuration register. 360 361 **/ 362 UINT8 363 EFIAPI 364 PciExpressBitFieldAndThenOr8 ( 365 IN UINTN Address, 366 IN UINTN StartBit, 367 IN UINTN EndBit, 368 IN UINT8 AndData, 369 IN UINT8 OrData 370 ); 371 372 /** 373 Reads a 16-bit PCI configuration register. 374 375 Reads and returns the 16-bit PCI configuration register specified by Address. 376 This function must guarantee that all PCI read and write operations are 377 serialized. 378 379 If Address > 0x0FFFFFFF, then ASSERT(). 380 If Address is not aligned on a 16-bit boundary, then ASSERT(). 381 382 @param Address Address that encodes the PCI Bus, Device, Function and 383 Register. 384 385 @return The read value from the PCI configuration register. 386 387 **/ 388 UINT16 389 EFIAPI 390 PciExpressRead16 ( 391 IN UINTN Address 392 ); 393 394 /** 395 Writes a 16-bit PCI configuration register. 396 397 Writes the 16-bit PCI configuration register specified by Address with the 398 value specified by Value. Value is returned. This function must guarantee 399 that all PCI read and write operations are serialized. 400 401 If Address > 0x0FFFFFFF, then ASSERT(). 402 If Address is not aligned on a 16-bit boundary, then ASSERT(). 403 404 @param Address Address that encodes the PCI Bus, Device, Function and 405 Register. 406 @param Value The value to write. 407 408 @return The value written to the PCI configuration register. 409 410 **/ 411 UINT16 412 EFIAPI 413 PciExpressWrite16 ( 414 IN UINTN Address, 415 IN UINT16 Value 416 ); 417 418 /** 419 Performs a bitwise OR of a 16-bit PCI configuration register with 420 a 16-bit value. 421 422 Reads the 16-bit PCI configuration register specified by Address, performs a 423 bitwise OR between the read result and the value specified by 424 OrData, and writes the result to the 16-bit PCI configuration register 425 specified by Address. The value written to the PCI configuration register is 426 returned. This function must guarantee that all PCI read and write operations 427 are serialized. 428 429 If Address > 0x0FFFFFFF, then ASSERT(). 430 If Address is not aligned on a 16-bit boundary, then ASSERT(). 431 432 @param Address Address that encodes the PCI Bus, Device, Function and 433 Register. 434 @param OrData The value to OR with the PCI configuration register. 435 436 @return The value written back to the PCI configuration register. 437 438 **/ 439 UINT16 440 EFIAPI 441 PciExpressOr16 ( 442 IN UINTN Address, 443 IN UINT16 OrData 444 ); 445 446 /** 447 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 448 value. 449 450 Reads the 16-bit PCI configuration register specified by Address, performs a 451 bitwise AND between the read result and the value specified by AndData, and 452 writes the result to the 16-bit PCI configuration register specified by 453 Address. The value written to the PCI configuration register is returned. 454 This function must guarantee that all PCI read and write operations are 455 serialized. 456 457 If Address > 0x0FFFFFFF, then ASSERT(). 458 If Address is not aligned on a 16-bit boundary, then ASSERT(). 459 460 @param Address Address that encodes the PCI Bus, Device, Function and 461 Register. 462 @param AndData The value to AND with the PCI configuration register. 463 464 @return The value written back to the PCI configuration register. 465 466 **/ 467 UINT16 468 EFIAPI 469 PciExpressAnd16 ( 470 IN UINTN Address, 471 IN UINT16 AndData 472 ); 473 474 /** 475 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 476 value, followed a bitwise OR with another 16-bit value. 477 478 Reads the 16-bit PCI configuration register specified by Address, performs a 479 bitwise AND between the read result and the value specified by AndData, 480 performs a bitwise OR between the result of the AND operation and 481 the value specified by OrData, and writes the result to the 16-bit PCI 482 configuration register specified by Address. The value written to the PCI 483 configuration register is returned. This function must guarantee that all PCI 484 read and write operations are serialized. 485 486 If Address > 0x0FFFFFFF, then ASSERT(). 487 If Address is not aligned on a 16-bit boundary, then ASSERT(). 488 489 @param Address Address that encodes the PCI Bus, Device, Function and 490 Register. 491 @param AndData The value to AND with the PCI configuration register. 492 @param OrData The value to OR with the result of the AND operation. 493 494 @return The value written back to the PCI configuration register. 495 496 **/ 497 UINT16 498 EFIAPI 499 PciExpressAndThenOr16 ( 500 IN UINTN Address, 501 IN UINT16 AndData, 502 IN UINT16 OrData 503 ); 504 505 /** 506 Reads a bit field of a PCI configuration register. 507 508 Reads the bit field in a 16-bit PCI configuration register. The bit field is 509 specified by the StartBit and the EndBit. The value of the bit field is 510 returned. 511 512 If Address > 0x0FFFFFFF, then ASSERT(). 513 If Address is not aligned on a 16-bit boundary, then ASSERT(). 514 If StartBit is greater than 15, then ASSERT(). 515 If EndBit is greater than 15, then ASSERT(). 516 If EndBit is less than StartBit, then ASSERT(). 517 518 @param Address PCI configuration register to read. 519 @param StartBit The ordinal of the least significant bit in the bit field. 520 Range 0..15. 521 @param EndBit The ordinal of the most significant bit in the bit field. 522 Range 0..15. 523 524 @return The value of the bit field read from the PCI configuration register. 525 526 **/ 527 UINT16 528 EFIAPI 529 PciExpressBitFieldRead16 ( 530 IN UINTN Address, 531 IN UINTN StartBit, 532 IN UINTN EndBit 533 ); 534 535 /** 536 Writes a bit field to a PCI configuration register. 537 538 Writes Value to the bit field of the PCI configuration register. The bit 539 field is specified by the StartBit and the EndBit. All other bits in the 540 destination PCI configuration register are preserved. The new value of the 541 16-bit register is returned. 542 543 If Address > 0x0FFFFFFF, then ASSERT(). 544 If Address is not aligned on a 16-bit boundary, then ASSERT(). 545 If StartBit is greater than 15, then ASSERT(). 546 If EndBit is greater than 15, then ASSERT(). 547 If EndBit is less than StartBit, then ASSERT(). 548 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 549 550 @param Address PCI configuration register to write. 551 @param StartBit The ordinal of the least significant bit in the bit field. 552 Range 0..15. 553 @param EndBit The ordinal of the most significant bit in the bit field. 554 Range 0..15. 555 @param Value New value of the bit field. 556 557 @return The value written back to the PCI configuration register. 558 559 **/ 560 UINT16 561 EFIAPI 562 PciExpressBitFieldWrite16 ( 563 IN UINTN Address, 564 IN UINTN StartBit, 565 IN UINTN EndBit, 566 IN UINT16 Value 567 ); 568 569 /** 570 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and 571 writes the result back to the bit field in the 16-bit port. 572 573 Reads the 16-bit PCI configuration register specified by Address, performs a 574 bitwise OR between the read result and the value specified by 575 OrData, and writes the result to the 16-bit PCI configuration register 576 specified by Address. The value written to the PCI configuration register is 577 returned. This function must guarantee that all PCI read and write operations 578 are serialized. Extra left bits in OrData are stripped. 579 580 If Address > 0x0FFFFFFF, then ASSERT(). 581 If Address is not aligned on a 16-bit boundary, then ASSERT(). 582 If StartBit is greater than 15, then ASSERT(). 583 If EndBit is greater than 15, then ASSERT(). 584 If EndBit is less than StartBit, then ASSERT(). 585 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 586 587 @param Address PCI configuration register to write. 588 @param StartBit The ordinal of the least significant bit in the bit field. 589 Range 0..15. 590 @param EndBit The ordinal of the most significant bit in the bit field. 591 Range 0..15. 592 @param OrData The value to OR with the PCI configuration register. 593 594 @return The value written back to the PCI configuration register. 595 596 **/ 597 UINT16 598 EFIAPI 599 PciExpressBitFieldOr16 ( 600 IN UINTN Address, 601 IN UINTN StartBit, 602 IN UINTN EndBit, 603 IN UINT16 OrData 604 ); 605 606 /** 607 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise 608 AND, and writes the result back to the bit field in the 16-bit register. 609 610 Reads the 16-bit PCI configuration register specified by Address, performs a 611 bitwise AND between the read result and the value specified by AndData, and 612 writes the result to the 16-bit PCI configuration register specified by 613 Address. The value written to the PCI configuration register is returned. 614 This function must guarantee that all PCI read and write operations are 615 serialized. Extra left bits in AndData are stripped. 616 617 If Address > 0x0FFFFFFF, then ASSERT(). 618 If Address is not aligned on a 16-bit boundary, then ASSERT(). 619 If StartBit is greater than 15, then ASSERT(). 620 If EndBit is greater than 15, then ASSERT(). 621 If EndBit is less than StartBit, then ASSERT(). 622 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 623 624 @param Address PCI configuration register to write. 625 @param StartBit The ordinal of the least significant bit in the bit field. 626 Range 0..15. 627 @param EndBit The ordinal of the most significant bit in the bit field. 628 Range 0..15. 629 @param AndData The value to AND with the PCI configuration register. 630 631 @return The value written back to the PCI configuration register. 632 633 **/ 634 UINT16 635 EFIAPI 636 PciExpressBitFieldAnd16 ( 637 IN UINTN Address, 638 IN UINTN StartBit, 639 IN UINTN EndBit, 640 IN UINT16 AndData 641 ); 642 643 /** 644 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a 645 bitwise OR, and writes the result back to the bit field in the 646 16-bit port. 647 648 Reads the 16-bit PCI configuration register specified by Address, performs a 649 bitwise AND followed by a bitwise OR between the read result and 650 the value specified by AndData, and writes the result to the 16-bit PCI 651 configuration register specified by Address. The value written to the PCI 652 configuration register is returned. This function must guarantee that all PCI 653 read and write operations are serialized. Extra left bits in both AndData and 654 OrData are stripped. 655 656 If Address > 0x0FFFFFFF, then ASSERT(). 657 If Address is not aligned on a 16-bit boundary, then ASSERT(). 658 If StartBit is greater than 15, then ASSERT(). 659 If EndBit is greater than 15, then ASSERT(). 660 If EndBit is less than StartBit, then ASSERT(). 661 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 662 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 663 664 @param Address PCI configuration register to write. 665 @param StartBit The ordinal of the least significant bit in the bit field. 666 Range 0..15. 667 @param EndBit The ordinal of the most significant bit in the bit field. 668 Range 0..15. 669 @param AndData The value to AND with the PCI configuration register. 670 @param OrData The value to OR with the result of the AND operation. 671 672 @return The value written back to the PCI configuration register. 673 674 **/ 675 UINT16 676 EFIAPI 677 PciExpressBitFieldAndThenOr16 ( 678 IN UINTN Address, 679 IN UINTN StartBit, 680 IN UINTN EndBit, 681 IN UINT16 AndData, 682 IN UINT16 OrData 683 ); 684 685 /** 686 Reads a 32-bit PCI configuration register. 687 688 Reads and returns the 32-bit PCI configuration register specified by Address. 689 This function must guarantee that all PCI read and write operations are 690 serialized. 691 692 If Address > 0x0FFFFFFF, then ASSERT(). 693 If Address is not aligned on a 32-bit boundary, then ASSERT(). 694 695 @param Address Address that encodes the PCI Bus, Device, Function and 696 Register. 697 698 @return The read value from the PCI configuration register. 699 700 **/ 701 UINT32 702 EFIAPI 703 PciExpressRead32 ( 704 IN UINTN Address 705 ); 706 707 /** 708 Writes a 32-bit PCI configuration register. 709 710 Writes the 32-bit PCI configuration register specified by Address with the 711 value specified by Value. Value is returned. This function must guarantee 712 that all PCI read and write operations are serialized. 713 714 If Address > 0x0FFFFFFF, then ASSERT(). 715 If Address is not aligned on a 32-bit boundary, then ASSERT(). 716 717 @param Address Address that encodes the PCI Bus, Device, Function and 718 Register. 719 @param Value The value to write. 720 721 @return The value written to the PCI configuration register. 722 723 **/ 724 UINT32 725 EFIAPI 726 PciExpressWrite32 ( 727 IN UINTN Address, 728 IN UINT32 Value 729 ); 730 731 /** 732 Performs a bitwise OR of a 32-bit PCI configuration register with 733 a 32-bit value. 734 735 Reads the 32-bit PCI configuration register specified by Address, performs a 736 bitwise OR between the read result and the value specified by 737 OrData, and writes the result to the 32-bit PCI configuration register 738 specified by Address. The value written to the PCI configuration register is 739 returned. This function must guarantee that all PCI read and write operations 740 are serialized. 741 742 If Address > 0x0FFFFFFF, then ASSERT(). 743 If Address is not aligned on a 32-bit boundary, then ASSERT(). 744 745 @param Address Address that encodes the PCI Bus, Device, Function and 746 Register. 747 @param OrData The value to OR with the PCI configuration register. 748 749 @return The value written back to the PCI configuration register. 750 751 **/ 752 UINT32 753 EFIAPI 754 PciExpressOr32 ( 755 IN UINTN Address, 756 IN UINT32 OrData 757 ); 758 759 /** 760 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 761 value. 762 763 Reads the 32-bit PCI configuration register specified by Address, performs a 764 bitwise AND between the read result and the value specified by AndData, and 765 writes the result to the 32-bit PCI configuration register specified by 766 Address. The value written to the PCI configuration register is returned. 767 This function must guarantee that all PCI read and write operations are 768 serialized. 769 770 If Address > 0x0FFFFFFF, then ASSERT(). 771 If Address is not aligned on a 32-bit boundary, then ASSERT(). 772 773 @param Address Address that encodes the PCI Bus, Device, Function and 774 Register. 775 @param AndData The value to AND with the PCI configuration register. 776 777 @return The value written back to the PCI configuration register. 778 779 **/ 780 UINT32 781 EFIAPI 782 PciExpressAnd32 ( 783 IN UINTN Address, 784 IN UINT32 AndData 785 ); 786 787 /** 788 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 789 value, followed a bitwise OR with another 32-bit value. 790 791 Reads the 32-bit PCI configuration register specified by Address, performs a 792 bitwise AND between the read result and the value specified by AndData, 793 performs a bitwise OR between the result of the AND operation and 794 the value specified by OrData, and writes the result to the 32-bit PCI 795 configuration register specified by Address. The value written to the PCI 796 configuration register is returned. This function must guarantee that all PCI 797 read and write operations are serialized. 798 799 If Address > 0x0FFFFFFF, then ASSERT(). 800 If Address is not aligned on a 32-bit boundary, then ASSERT(). 801 802 @param Address Address that encodes the PCI Bus, Device, Function and 803 Register. 804 @param AndData The value to AND with the PCI configuration register. 805 @param OrData The value to OR with the result of the AND operation. 806 807 @return The value written back to the PCI configuration register. 808 809 **/ 810 UINT32 811 EFIAPI 812 PciExpressAndThenOr32 ( 813 IN UINTN Address, 814 IN UINT32 AndData, 815 IN UINT32 OrData 816 ); 817 818 /** 819 Reads a bit field of a PCI configuration register. 820 821 Reads the bit field in a 32-bit PCI configuration register. The bit field is 822 specified by the StartBit and the EndBit. The value of the bit field is 823 returned. 824 825 If Address > 0x0FFFFFFF, then ASSERT(). 826 If Address is not aligned on a 32-bit boundary, then ASSERT(). 827 If StartBit is greater than 31, then ASSERT(). 828 If EndBit is greater than 31, then ASSERT(). 829 If EndBit is less than StartBit, then ASSERT(). 830 831 @param Address PCI configuration register to read. 832 @param StartBit The ordinal of the least significant bit in the bit field. 833 Range 0..31. 834 @param EndBit The ordinal of the most significant bit in the bit field. 835 Range 0..31. 836 837 @return The value of the bit field read from the PCI configuration register. 838 839 **/ 840 UINT32 841 EFIAPI 842 PciExpressBitFieldRead32 ( 843 IN UINTN Address, 844 IN UINTN StartBit, 845 IN UINTN EndBit 846 ); 847 848 /** 849 Writes a bit field to a PCI configuration register. 850 851 Writes Value to the bit field of the PCI configuration register. The bit 852 field is specified by the StartBit and the EndBit. All other bits in the 853 destination PCI configuration register are preserved. The new value of the 854 32-bit register is returned. 855 856 If Address > 0x0FFFFFFF, then ASSERT(). 857 If Address is not aligned on a 32-bit boundary, then ASSERT(). 858 If StartBit is greater than 31, then ASSERT(). 859 If EndBit is greater than 31, then ASSERT(). 860 If EndBit is less than StartBit, then ASSERT(). 861 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 862 863 @param Address PCI configuration register to write. 864 @param StartBit The ordinal of the least significant bit in the bit field. 865 Range 0..31. 866 @param EndBit The ordinal of the most significant bit in the bit field. 867 Range 0..31. 868 @param Value New value of the bit field. 869 870 @return The value written back to the PCI configuration register. 871 872 **/ 873 UINT32 874 EFIAPI 875 PciExpressBitFieldWrite32 ( 876 IN UINTN Address, 877 IN UINTN StartBit, 878 IN UINTN EndBit, 879 IN UINT32 Value 880 ); 881 882 /** 883 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and 884 writes the result back to the bit field in the 32-bit port. 885 886 Reads the 32-bit PCI configuration register specified by Address, performs a 887 bitwise OR between the read result and the value specified by 888 OrData, and writes the result to the 32-bit PCI configuration register 889 specified by Address. The value written to the PCI configuration register is 890 returned. This function must guarantee that all PCI read and write operations 891 are serialized. Extra left bits in OrData are stripped. 892 893 If Address > 0x0FFFFFFF, then ASSERT(). 894 If Address is not aligned on a 32-bit boundary, then ASSERT(). 895 If StartBit is greater than 31, then ASSERT(). 896 If EndBit is greater than 31, then ASSERT(). 897 If EndBit is less than StartBit, then ASSERT(). 898 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 899 900 @param Address PCI configuration register to write. 901 @param StartBit The ordinal of the least significant bit in the bit field. 902 Range 0..31. 903 @param EndBit The ordinal of the most significant bit in the bit field. 904 Range 0..31. 905 @param OrData The value to OR with the PCI configuration register. 906 907 @return The value written back to the PCI configuration register. 908 909 **/ 910 UINT32 911 EFIAPI 912 PciExpressBitFieldOr32 ( 913 IN UINTN Address, 914 IN UINTN StartBit, 915 IN UINTN EndBit, 916 IN UINT32 OrData 917 ); 918 919 /** 920 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise 921 AND, and writes the result back to the bit field in the 32-bit register. 922 923 Reads the 32-bit PCI configuration register specified by Address, performs a 924 bitwise AND between the read result and the value specified by AndData, and 925 writes the result to the 32-bit PCI configuration register specified by 926 Address. The value written to the PCI configuration register is returned. 927 This function must guarantee that all PCI read and write operations are 928 serialized. Extra left bits in AndData are stripped. 929 930 If Address > 0x0FFFFFFF, then ASSERT(). 931 If Address is not aligned on a 32-bit boundary, then ASSERT(). 932 If StartBit is greater than 31, then ASSERT(). 933 If EndBit is greater than 31, then ASSERT(). 934 If EndBit is less than StartBit, then ASSERT(). 935 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 936 937 @param Address PCI configuration register to write. 938 @param StartBit The ordinal of the least significant bit in the bit field. 939 Range 0..31. 940 @param EndBit The ordinal of the most significant bit in the bit field. 941 Range 0..31. 942 @param AndData The value to AND with the PCI configuration register. 943 944 @return The value written back to the PCI configuration register. 945 946 **/ 947 UINT32 948 EFIAPI 949 PciExpressBitFieldAnd32 ( 950 IN UINTN Address, 951 IN UINTN StartBit, 952 IN UINTN EndBit, 953 IN UINT32 AndData 954 ); 955 956 /** 957 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a 958 bitwise OR, and writes the result back to the bit field in the 959 32-bit port. 960 961 Reads the 32-bit PCI configuration register specified by Address, performs a 962 bitwise AND followed by a bitwise OR between the read result and 963 the value specified by AndData, and writes the result to the 32-bit PCI 964 configuration register specified by Address. The value written to the PCI 965 configuration register is returned. This function must guarantee that all PCI 966 read and write operations are serialized. Extra left bits in both AndData and 967 OrData are stripped. 968 969 If Address > 0x0FFFFFFF, then ASSERT(). 970 If Address is not aligned on a 32-bit boundary, then ASSERT(). 971 If StartBit is greater than 31, then ASSERT(). 972 If EndBit is greater than 31, then ASSERT(). 973 If EndBit is less than StartBit, then ASSERT(). 974 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 975 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 976 977 @param Address PCI configuration register to write. 978 @param StartBit The ordinal of the least significant bit in the bit field. 979 Range 0..31. 980 @param EndBit The ordinal of the most significant bit in the bit field. 981 Range 0..31. 982 @param AndData The value to AND with the PCI configuration register. 983 @param OrData The value to OR with the result of the AND operation. 984 985 @return The value written back to the PCI configuration register. 986 987 **/ 988 UINT32 989 EFIAPI 990 PciExpressBitFieldAndThenOr32 ( 991 IN UINTN Address, 992 IN UINTN StartBit, 993 IN UINTN EndBit, 994 IN UINT32 AndData, 995 IN UINT32 OrData 996 ); 997 998 /** 999 Reads a range of PCI configuration registers into a caller supplied buffer. 1000 1001 Reads the range of PCI configuration registers specified by StartAddress and 1002 Size into the buffer specified by Buffer. This function only allows the PCI 1003 configuration registers from a single PCI function to be read. Size is 1004 returned. When possible 32-bit PCI configuration read cycles are used to read 1005 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit 1006 and 16-bit PCI configuration read cycles may be used at the beginning and the 1007 end of the range. 1008 1009 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1010 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1011 If Size > 0 and Buffer is NULL, then ASSERT(). 1012 1013 @param StartAddress Starting address that encodes the PCI Bus, Device, 1014 Function and Register. 1015 @param Size Size in bytes of the transfer. 1016 @param Buffer Pointer to a buffer receiving the data read. 1017 1018 @return Size read data from StartAddress. 1019 1020 **/ 1021 UINTN 1022 EFIAPI 1023 PciExpressReadBuffer ( 1024 IN UINTN StartAddress, 1025 IN UINTN Size, 1026 OUT VOID *Buffer 1027 ); 1028 1029 /** 1030 Copies the data in a caller supplied buffer to a specified range of PCI 1031 configuration space. 1032 1033 Writes the range of PCI configuration registers specified by StartAddress and 1034 Size from the buffer specified by Buffer. This function only allows the PCI 1035 configuration registers from a single PCI function to be written. Size is 1036 returned. When possible 32-bit PCI configuration write cycles are used to 1037 write from StartAdress to StartAddress + Size. Due to alignment restrictions, 1038 8-bit and 16-bit PCI configuration write cycles may be used at the beginning 1039 and the end of the range. 1040 1041 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1042 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1043 If Size > 0 and Buffer is NULL, then ASSERT(). 1044 1045 @param StartAddress Starting address that encodes the PCI Bus, Device, 1046 Function and Register. 1047 @param Size Size in bytes of the transfer. 1048 @param Buffer Pointer to a buffer containing the data to write. 1049 1050 @return Size written to StartAddress. 1051 1052 **/ 1053 UINTN 1054 EFIAPI 1055 PciExpressWriteBuffer ( 1056 IN UINTN StartAddress, 1057 IN UINTN Size, 1058 IN VOID *Buffer 1059 ); 1060 1061 #endif 1062
