1 /// @file 2 /// Contains an implementation of CallPalProcStacked on Itanium-based 3 /// architecture. 4 /// 5 /// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> 6 /// This program and the accompanying materials 7 /// are licensed and made available under the terms and conditions of the BSD License 8 /// which accompanies this distribution. The full text of the license may be found at 9 /// http://opensource.org/licenses/bsd-license.php. 10 /// 11 /// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 /// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 /// 14 /// Module Name: AsmCpuMisc.s 15 /// 16 /// 17 18 19 .text 20 .proc CpuBreakpoint 21 .type CpuBreakpoint, @function 22 23 CpuBreakpoint:: 24 break.i 0;; 25 br.ret.dpnt b0;; 26 27 .endp CpuBreakpoint 28 29 .proc MemoryFence 30 .type MemoryFence, @function 31 32 MemoryFence:: 33 mf;; // memory access ordering 34 35 // do we need the mf.a also here? 36 mf.a // wait for any IO to complete? 37 38 // not sure if we need serialization here, just put it, in case... 39 40 srlz.d;; 41 srlz.i;; 42 43 br.ret.dpnt b0;; 44 .endp MemoryFence 45 46 .proc DisableInterrupts 47 .type DisableInterrupts, @function 48 49 DisableInterrupts:: 50 rsm 0x4000 51 srlz.d;; 52 br.ret.dpnt b0;; 53 54 .endp DisableInterrupts 55 56 .proc EnableInterrupts 57 .type EnableInterrupts, @function 58 59 EnableInterrupts:: 60 ssm 0x4000 61 srlz.d;; 62 br.ret.dpnt b0;; 63 64 .endp EnableInterrupts 65 66 .proc EnableDisableInterrupts 67 .type EnableDisableInterrupts, @function 68 69 EnableDisableInterrupts:: 70 ssm 0x4000 71 srlz.d;; 72 srlz.i;; 73 rsm 0x4000 74 srlz.d;; 75 76 br.ret.dpnt b0;; 77 78 .endp EnableDisableInterrupts 79 80
