1 /** @file 2 Internal function to get spin lock alignment. 3 4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php. 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #include "BaseSynchronizationLibInternals.h" 16 17 /** 18 Internal function to retrieve the architecture specific spin lock alignment 19 requirements for optimal spin lock performance. 20 21 @return The architecture specific spin lock alignment. 22 23 **/ 24 UINTN 25 InternalGetSpinLockProperties ( 26 VOID 27 ) 28 { 29 UINT32 RegEax; 30 UINT32 RegEbx; 31 UINTN FamilyId; 32 UINTN ModelId; 33 UINTN CacheLineSize; 34 35 // 36 // Retrieve CPUID Version Information 37 // 38 AsmCpuid (0x01, &RegEax, &RegEbx, NULL, NULL); 39 // 40 // EBX: Bits 15 - 08: CLFLUSH line size (Value * 8 = cache line size) 41 // 42 CacheLineSize = ((RegEbx >> 8) & 0xff) * 8; 43 // 44 // Retrieve CPU Family and Model 45 // 46 FamilyId = (RegEax >> 8) & 0xf; 47 ModelId = (RegEax >> 4) & 0xf; 48 if (FamilyId == 0x0f) { 49 // 50 // In processors based on Intel NetBurst microarchitecture, use two cache lines 51 // 52 ModelId = ModelId | ((RegEax >> 12) & 0xf0); 53 if (ModelId <= 0x04 || ModelId == 0x06) { 54 CacheLineSize *= 2; 55 } 56 } 57 58 if (CacheLineSize < 32) { 59 CacheLineSize = 32; 60 } 61 62 return CacheLineSize; 63 } 64 65
