1 /** @file 2 This file describes the contents of the ACPI Fixed ACPI Description Table 3 (FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h. 4 All changes to the FADT contents should be done in this file. 5 6 Copyright (c) 2013-2015 Intel Corporation. 7 8 This program and the accompanying materials 9 are licensed and made available under the terms and conditions of the BSD License 10 which accompanies this distribution. The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php 12 13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 15 16 **/ 17 18 #include "Fadt.h" 19 20 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = { 21 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, 22 sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE), 23 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, 24 0, // to make sum of entire table == 0 25 EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field 26 EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long) 27 EFI_ACPI_OEM_REVISION, // OEM revision number 28 EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID 29 EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number 30 0, // Physical addesss of FACS 31 0, // Physical address of DSDT 32 INT_MODEL, // System Interrupt Model 33 RESERVED, // reserved 34 SCI_INT_VECTOR, // System vector of SCI interrupt 35 SMI_CMD_IO_PORT, // Port address of SMI command port 36 ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI 37 ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI 38 S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state 39 RESERVED, // reserved - must be zero 40 PM1a_EVT_BLK_ADDRESS, // Port address of Power Mgt 1a Event Reg Blk 41 PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk 42 PM1a_CNT_BLK_ADDRESS, // Port address of Power Mgt 1a Ctrl Reg Blk 43 PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk 44 PM2_CNT_BLK_ADDRESS, // Port address of Power Mgt 2 Ctrl Reg Blk 45 PM_TMR_BLK_ADDRESS, // Port address of Power Mgt Timer Ctrl Reg Blk 46 GPE0_BLK_ADDRESS, // Port addr of General Purpose Event 0 Reg Blk 47 GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk 48 PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk 49 PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk 50 PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk 51 PM_TM_LEN, // Byte Length of ports at pm_tm_blk 52 GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk 53 GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk 54 GPE1_BASE, // offset in gpe model where gpe1 events start 55 RESERVED, // reserved 56 P_LVL2_LAT, // worst case HW latency to enter/exit C2 state 57 P_LVL3_LAT, // worst case HW latency to enter/exit C3 state 58 FLUSH_SIZE, // Size of area read to flush caches 59 FLUSH_STRIDE, // Stride used in flushing caches 60 DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg 61 DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg 62 DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM 63 MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM 64 CENTURY, // index to century in RTC CMOS RAM 65 RESERVED, // reserved 66 RESERVED, // reserved 67 RESERVED, // reserved 68 FLAG 69 }; 70 71 VOID* 72 ReferenceAcpiTable ( 73 VOID 74 ) 75 76 { 77 // 78 // Reference the table being generated to prevent the optimizer from removing the 79 // data structure from the exeutable 80 // 81 return (VOID*)&FADT; 82 } 83
