1 /** @file 2 Header file for AHCI mode of ATA host controller. 3 4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 16 #ifndef __OPAL_PASSWORD_AHCI_MODE_H__ 17 #define __OPAL_PASSWORD_AHCI_MODE_H__ 18 19 // 20 // OPAL LIBRARY CALLBACKS 21 // 22 #define ATA_COMMAND_TRUSTED_RECEIVE 0x5C 23 #define ATA_COMMAND_TRUSTED_SEND 0x5E 24 25 // 26 // ATA TRUSTED commands express transfer Length in 512 byte multiple 27 // 28 #define ATA_TRUSTED_TRANSFER_LENGTH_MULTIPLE 512 29 #define ATA_DEVICE_LBA 0x40 ///< Set for commands with LBA (rather than CHS) addresses 30 31 32 #define EFI_AHCI_BAR_INDEX 0x05 33 34 #define EFI_AHCI_CAPABILITY_OFFSET 0x0000 35 #define EFI_AHCI_CAP_SAM BIT18 36 #define EFI_AHCI_GHC_OFFSET 0x0004 37 #define EFI_AHCI_GHC_RESET BIT0 38 #define EFI_AHCI_GHC_IE BIT1 39 #define EFI_AHCI_GHC_ENABLE BIT31 40 #define EFI_AHCI_IS_OFFSET 0x0008 41 #define EFI_AHCI_PI_OFFSET 0x000C 42 43 typedef struct { 44 UINT32 Lower32; 45 UINT32 Upper32; 46 } DATA_32; 47 48 typedef union { 49 DATA_32 Uint32; 50 UINT64 Uint64; 51 } DATA_64; 52 53 // 54 // Each PRDT entry can point to a memory block up to 4M byte 55 // 56 #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000 57 58 #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device 59 #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20 60 #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host 61 #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20 62 #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host 63 #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4 64 #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional 65 #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28 66 #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional 67 #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional 68 #define EFI_AHCI_FIS_BIST_LENGTH 12 69 #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host 70 #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20 71 #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host 72 #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8 73 74 #define EFI_AHCI_D2H_FIS_OFFSET 0x40 75 #define EFI_AHCI_DMA_FIS_OFFSET 0x00 76 #define EFI_AHCI_PIO_FIS_OFFSET 0x20 77 #define EFI_AHCI_SDB_FIS_OFFSET 0x58 78 #define EFI_AHCI_FIS_TYPE_MASK 0xFF 79 #define EFI_AHCI_U_FIS_OFFSET 0x60 80 81 // 82 // Port register 83 // 84 #define EFI_AHCI_PORT_START 0x0100 85 #define EFI_AHCI_PORT_REG_WIDTH 0x0080 86 #define EFI_AHCI_PORT_CLB 0x0000 87 #define EFI_AHCI_PORT_CLBU 0x0004 88 #define EFI_AHCI_PORT_FB 0x0008 89 #define EFI_AHCI_PORT_FBU 0x000C 90 #define EFI_AHCI_PORT_IS 0x0010 91 #define EFI_AHCI_PORT_IS_DHRS BIT0 92 #define EFI_AHCI_PORT_IS_PSS BIT1 93 #define EFI_AHCI_PORT_IS_SSS BIT2 94 #define EFI_AHCI_PORT_IS_SDBS BIT3 95 #define EFI_AHCI_PORT_IS_UFS BIT4 96 #define EFI_AHCI_PORT_IS_DPS BIT5 97 #define EFI_AHCI_PORT_IS_PCS BIT6 98 #define EFI_AHCI_PORT_IS_DIS BIT7 99 #define EFI_AHCI_PORT_IS_PRCS BIT22 100 #define EFI_AHCI_PORT_IS_IPMS BIT23 101 #define EFI_AHCI_PORT_IS_OFS BIT24 102 #define EFI_AHCI_PORT_IS_INFS BIT26 103 #define EFI_AHCI_PORT_IS_IFS BIT27 104 #define EFI_AHCI_PORT_IS_HBDS BIT28 105 #define EFI_AHCI_PORT_IS_HBFS BIT29 106 #define EFI_AHCI_PORT_IS_TFES BIT30 107 #define EFI_AHCI_PORT_IS_CPDS BIT31 108 #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF 109 #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F 110 111 #define EFI_AHCI_PORT_IE 0x0014 112 #define EFI_AHCI_PORT_CMD 0x0018 113 #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE 114 #define EFI_AHCI_PORT_CMD_ST BIT0 115 #define EFI_AHCI_PORT_CMD_SUD BIT1 116 #define EFI_AHCI_PORT_CMD_POD BIT2 117 #define EFI_AHCI_PORT_CMD_COL BIT3 118 #define EFI_AHCI_PORT_CMD_CR BIT15 119 #define EFI_AHCI_PORT_CMD_FRE BIT4 120 #define EFI_AHCI_PORT_CMD_FR BIT14 121 #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL) 122 #define EFI_AHCI_PORT_CMD_PMA BIT17 123 #define EFI_AHCI_PORT_CMD_HPCP BIT18 124 #define EFI_AHCI_PORT_CMD_MPSP BIT19 125 #define EFI_AHCI_PORT_CMD_CPD BIT20 126 #define EFI_AHCI_PORT_CMD_ESP BIT21 127 #define EFI_AHCI_PORT_CMD_ATAPI BIT24 128 #define EFI_AHCI_PORT_CMD_DLAE BIT25 129 #define EFI_AHCI_PORT_CMD_ALPE BIT26 130 #define EFI_AHCI_PORT_CMD_ASP BIT27 131 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31) 132 #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 ) 133 #define EFI_AHCI_PORT_TFD 0x0020 134 #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0) 135 #define EFI_AHCI_PORT_TFD_BSY BIT7 136 #define EFI_AHCI_PORT_TFD_DRQ BIT3 137 #define EFI_AHCI_PORT_TFD_ERR BIT0 138 #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00 139 #define EFI_AHCI_PORT_SIG 0x0024 140 #define EFI_AHCI_PORT_SSTS 0x0028 141 #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F 142 #define EFI_AHCI_PORT_SSTS_DET 0x0001 143 #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003 144 #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0 145 #define EFI_AHCI_PORT_SCTL 0x002C 146 #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F 147 #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK) 148 #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001 149 #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003 150 #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0 151 #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00 152 #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300 153 #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100 154 #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200 155 #define EFI_AHCI_PORT_SERR 0x0030 156 #define EFI_AHCI_PORT_SERR_RDIE BIT0 157 #define EFI_AHCI_PORT_SERR_RCE BIT1 158 #define EFI_AHCI_PORT_SERR_TDIE BIT8 159 #define EFI_AHCI_PORT_SERR_PCDIE BIT9 160 #define EFI_AHCI_PORT_SERR_PE BIT10 161 #define EFI_AHCI_PORT_SERR_IE BIT11 162 #define EFI_AHCI_PORT_SERR_PRC BIT16 163 #define EFI_AHCI_PORT_SERR_PIE BIT17 164 #define EFI_AHCI_PORT_SERR_CW BIT18 165 #define EFI_AHCI_PORT_SERR_BDE BIT19 166 #define EFI_AHCI_PORT_SERR_DE BIT20 167 #define EFI_AHCI_PORT_SERR_CRCE BIT21 168 #define EFI_AHCI_PORT_SERR_HE BIT22 169 #define EFI_AHCI_PORT_SERR_LSE BIT23 170 #define EFI_AHCI_PORT_SERR_TSTE BIT24 171 #define EFI_AHCI_PORT_SERR_UFT BIT25 172 #define EFI_AHCI_PORT_SERR_EX BIT26 173 #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF 174 #define EFI_AHCI_PORT_SACT 0x0034 175 #define EFI_AHCI_PORT_CI 0x0038 176 #define EFI_AHCI_PORT_SNTF 0x003C 177 178 179 #pragma pack(1) 180 // 181 // Command List structure includes total 32 entries. 182 // The entry Data structure is listed at the following. 183 // 184 typedef struct { 185 UINT32 AhciCmdCfl:5; //Command FIS Length 186 UINT32 AhciCmdA:1; //ATAPI 187 UINT32 AhciCmdW:1; //Write 188 UINT32 AhciCmdP:1; //Prefetchable 189 UINT32 AhciCmdR:1; //Reset 190 UINT32 AhciCmdB:1; //BIST 191 UINT32 AhciCmdC:1; //Clear Busy upon R_OK 192 UINT32 AhciCmdRsvd:1; 193 UINT32 AhciCmdPmp:4; //Port Multiplier Port 194 UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length 195 UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count 196 UINT32 AhciCmdCtba; //Command Table Descriptor Base Address 197 UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs 198 UINT32 AhciCmdRsvd1[4]; 199 } EFI_AHCI_COMMAND_LIST; 200 201 // 202 // This is a software constructed FIS. 203 // For Data transfer operations, this is the H2D Register FIS format as 204 // specified in the Serial ATA Revision 2.6 specification. 205 // 206 typedef struct { 207 UINT8 AhciCFisType; 208 UINT8 AhciCFisPmNum:4; 209 UINT8 AhciCFisRsvd:1; 210 UINT8 AhciCFisRsvd1:1; 211 UINT8 AhciCFisRsvd2:1; 212 UINT8 AhciCFisCmdInd:1; 213 UINT8 AhciCFisCmd; 214 UINT8 AhciCFisFeature; 215 UINT8 AhciCFisSecNum; 216 UINT8 AhciCFisClyLow; 217 UINT8 AhciCFisClyHigh; 218 UINT8 AhciCFisDevHead; 219 UINT8 AhciCFisSecNumExp; 220 UINT8 AhciCFisClyLowExp; 221 UINT8 AhciCFisClyHighExp; 222 UINT8 AhciCFisFeatureExp; 223 UINT8 AhciCFisSecCount; 224 UINT8 AhciCFisSecCountExp; 225 UINT8 AhciCFisRsvd3; 226 UINT8 AhciCFisControl; 227 UINT8 AhciCFisRsvd4[4]; 228 UINT8 AhciCFisRsvd5[44]; 229 } EFI_AHCI_COMMAND_FIS; 230 231 // 232 // ACMD: ATAPI command (12 or 16 bytes) 233 // 234 typedef struct { 235 UINT8 AtapiCmd[0x10]; 236 } EFI_AHCI_ATAPI_COMMAND; 237 238 // 239 // Physical Region Descriptor Table includes up to 65535 entries 240 // The entry Data structure is listed at the following. 241 // the actual entry number comes from the PRDTL field in the command 242 // list entry for this command slot. 243 // 244 typedef struct { 245 UINT32 AhciPrdtDba; //Data Base Address 246 UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs 247 UINT32 AhciPrdtRsvd; 248 UINT32 AhciPrdtDbc:22; //Data Byte Count 249 UINT32 AhciPrdtRsvd1:9; 250 UINT32 AhciPrdtIoc:1; //Interrupt on Completion 251 } EFI_AHCI_COMMAND_PRDT; 252 253 // 254 // Command table Data strucute which is pointed to by the entry in the command list 255 // 256 typedef struct { 257 EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS. 258 EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd. 259 UINT8 Reserved[0x30]; 260 EFI_AHCI_COMMAND_PRDT PrdtTable; // The scatter/gather list for Data transfer 261 } EFI_AHCI_COMMAND_TABLE; 262 263 // 264 // Received FIS structure 265 // 266 typedef struct { 267 UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00 268 UINT8 AhciDmaSetupFisRsvd[0x04]; 269 UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20 270 UINT8 AhciPioSetupFisRsvd[0x0C]; 271 UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40 272 UINT8 AhciD2HRegisterFisRsvd[0x04]; 273 UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58 274 UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60 275 UINT8 AhciUnknownFisRsvd[0x60]; 276 } EFI_AHCI_RECEIVED_FIS; 277 278 #pragma pack() 279 280 typedef struct { 281 EFI_AHCI_RECEIVED_FIS *AhciRFis; 282 EFI_AHCI_COMMAND_LIST *AhciCmdList; 283 EFI_AHCI_COMMAND_TABLE *AhciCommandTable; 284 } EFI_AHCI_REGISTERS; 285 286 extern EFI_AHCI_REGISTERS mAhciRegisters; 287 extern UINT32 mAhciBar; 288 289 /** 290 Send Buffer cmd to specific device. 291 292 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS. 293 @param Port The number of port. 294 @param PortMultiplier The timeout Value of stop. 295 @param Buffer The Data Buffer to store IDENTIFY PACKET Data. 296 297 @retval EFI_DEVICE_ERROR The cmd abort with error occurs. 298 @retval EFI_TIMEOUT The operation is time out. 299 @retval EFI_UNSUPPORTED The device is not ready for executing. 300 @retval EFI_SUCCESS The cmd executes successfully. 301 302 **/ 303 EFI_STATUS 304 EFIAPI 305 AhciIdentify ( 306 IN EFI_AHCI_REGISTERS *AhciRegisters, 307 IN UINT8 Port, 308 IN UINT8 PortMultiplier, 309 IN OUT ATA_IDENTIFY_DATA *Buffer 310 ); 311 312 /** 313 Get AHCI mode base address registers' Value. 314 315 @param[in] Bus The bus number of ata host controller. 316 @param[in] Device The device number of ata host controller. 317 @param[in] Function The function number of ata host controller. 318 319 @retval EFI_UNSUPPORTED Return this Value when the BARs is not IO type 320 @retval EFI_SUCCESS Get the Base address successfully 321 @retval Other Read the pci configureation Data error 322 323 **/ 324 EFI_STATUS 325 EFIAPI 326 GetAhciBaseAddress ( 327 IN UINTN Bus, 328 IN UINTN Device, 329 IN UINTN Function 330 ); 331 332 /** 333 Allocate transfer-related Data struct which is used at AHCI mode. 334 335 @retval EFI_OUT_OF_RESOURCE The allocation is failure. 336 @retval EFI_SUCCESS Successful to allocate memory. 337 338 **/ 339 EFI_STATUS 340 EFIAPI 341 AhciAllocateResource ( 342 VOID 343 ); 344 345 /** 346 Free allocated transfer-related Data struct which is used at AHCI mode. 347 348 **/ 349 VOID 350 EFIAPI 351 AhciFreeResource ( 352 VOID 353 ); 354 355 /** 356 Initialize ATA host controller at AHCI mode. 357 358 The function is designed to initialize ATA host controller. 359 360 @param[in] Port The port number to do initialization. 361 362 **/ 363 EFI_STATUS 364 EFIAPI 365 AhciModeInitialize ( 366 UINT8 Port 367 ); 368 369 /** 370 Start a PIO Data transfer on specific port. 371 372 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS. 373 @param Port The number of port. 374 @param PortMultiplier The timeout Value of stop. 375 @param AtapiCommand The atapi command will be used for the transfer. 376 @param AtapiCommandLength The Length of the atapi command. 377 @param Read The transfer direction. 378 @param AtaCommandBlock The EFI_ATA_COMMAND_BLOCK Data. 379 @param AtaStatusBlock The EFI_ATA_STATUS_BLOCK Data. 380 @param MemoryAddr The pointer to the Data Buffer. 381 @param DataCount The Data count to be transferred. 382 @param Timeout The timeout Value of non Data transfer. 383 384 @retval EFI_DEVICE_ERROR The PIO Data transfer abort with error occurs. 385 @retval EFI_TIMEOUT The operation is time out. 386 @retval EFI_UNSUPPORTED The device is not ready for transfer. 387 @retval EFI_SUCCESS The PIO Data transfer executes successfully. 388 389 **/ 390 EFI_STATUS 391 EFIAPI 392 AhciPioTransfer ( 393 IN EFI_AHCI_REGISTERS *AhciRegisters, 394 IN UINT8 Port, 395 IN UINT8 PortMultiplier, 396 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL, 397 IN UINT8 AtapiCommandLength, 398 IN BOOLEAN Read, 399 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock, 400 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock, 401 IN OUT VOID *MemoryAddr, 402 IN UINT32 DataCount, 403 IN UINT64 Timeout 404 ); 405 406 407 #endif 408 409
