1 /** @file 2 MSR Definitions for Pentium(R) 4 Processors. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.18. 21 22 **/ 23 24 #ifndef __PENTIUM_4_MSR_H__ 25 #define __PENTIUM_4_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range 31 Determination.". 32 33 @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006) 34 @param EAX Lower 32-bits of MSR value. 35 @param EDX Upper 32-bits of MSR value. 36 37 <b>Example usage</b> 38 @code 39 UINT64 Msr; 40 41 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE); 42 AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr); 43 @endcode 44 @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM. 45 **/ 46 #define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006 47 48 49 /** 50 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W) 51 Enables and disables processor features; (R) indicates current processor 52 configuration. 53 54 @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A) 55 @param EAX Lower 32-bits of MSR value. 56 Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER. 57 @param EDX Upper 32-bits of MSR value. 58 Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER. 59 60 <b>Example usage</b> 61 @code 62 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr; 63 64 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON); 65 AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64); 66 @endcode 67 @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM. 68 **/ 69 #define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A 70 71 /** 72 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON 73 **/ 74 typedef union { 75 /// 76 /// Individual bit fields 77 /// 78 struct { 79 /// 80 /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state 81 /// output is enabled (1) or disabled (0) as set by the strapping of SMI#. 82 /// The value in this bit is written on the deassertion of RESET#; the bit 83 /// is set to 1 when the address bus signal is asserted. 84 /// 85 UINT32 OutputTriStateEnabled:1; 86 /// 87 /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST 88 /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The 89 /// value in this bit is written on the deassertion of RESET#; the bit is 90 /// set to 1 when the address bus signal is asserted. 91 /// 92 UINT32 ExecuteBIST:1; 93 /// 94 /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue 95 /// depth for the system bus is 1 (1) or up to 12 (0) as set by the 96 /// strapping of A7#. The value in this bit is written on the deassertion 97 /// of RESET#; the bit is set to 1 when the address bus signal is asserted. 98 /// 99 UINT32 InOrderQueueDepth:1; 100 /// 101 /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR# 102 /// observation is enabled (0) or disabled (1) as determined by the 103 /// strapping of A9#. The value in this bit is written on the deassertion 104 /// of RESET#; the bit is set to 1 when the address bus signal is asserted. 105 /// 106 UINT32 MCERR_ObservationDisabled:1; 107 /// 108 /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT# 109 /// observation is enabled (0) or disabled (1) as determined by the 110 /// strapping of A10#. The value in this bit is written on the deassertion 111 /// of RESET#; the bit is set to 1 when the address bus signal is asserted. 112 /// 113 UINT32 BINIT_ObservationEnabled:1; 114 /// 115 /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID 116 /// value as set by the strapping of A12# and A11#. The logical cluster ID 117 /// value is written into the field on the deassertion of RESET#; the 118 /// field is set to 1 when the address bus signal is asserted. 119 /// 120 UINT32 APICClusterID:2; 121 /// 122 /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled 123 /// (0) or disabled (1) as set by the strapping of A15#. The value in this 124 /// bit is written on the deassertion of RESET#; the bit is set to 1 when 125 /// the address bus signal is asserted. 126 /// 127 UINT32 BusParkDisable:1; 128 UINT32 Reserved1:4; 129 /// 130 /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set 131 /// by the strapping of BR[3:0]. The logical ID value is written into the 132 /// field on the deassertion of RESET#; the field is set to 1 when the 133 /// address bus signal is asserted. 134 /// 135 UINT32 AgentID:2; 136 UINT32 Reserved2:18; 137 UINT32 Reserved3:32; 138 } Bits; 139 /// 140 /// All bit fields as a 32-bit value 141 /// 142 UINT32 Uint32; 143 /// 144 /// All bit fields as a 64-bit value 145 /// 146 UINT64 Uint64; 147 } MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER; 148 149 150 /** 151 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W) 152 Enables and disables processor features. 153 154 @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B) 155 @param EAX Lower 32-bits of MSR value. 156 Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER. 157 @param EDX Upper 32-bits of MSR value. 158 Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER. 159 160 <b>Example usage</b> 161 @code 162 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr; 163 164 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON); 165 AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64); 166 @endcode 167 @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM. 168 **/ 169 #define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B 170 171 /** 172 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON 173 **/ 174 typedef union { 175 /// 176 /// Individual bit fields 177 /// 178 struct { 179 /// 180 /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the 181 /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear 182 /// to disabled (0, default). 183 /// 184 UINT32 RCNT_SCNT:1; 185 /// 186 /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data 187 /// bus parity checking; clear to enable parity checking. 188 /// 189 UINT32 DataErrorCheckingDisable:1; 190 /// 191 /// [Bit 2] Response Error Checking Disable (R/W) Set to disable 192 /// (default); clear to enable. 193 /// 194 UINT32 ResponseErrorCheckingDisable:1; 195 /// 196 /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable 197 /// (default); clear to enable. 198 /// 199 UINT32 AddressRequestErrorCheckingDisable:1; 200 /// 201 /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving 202 /// for initiator bus requests (default); clear to enable. 203 /// 204 UINT32 InitiatorMCERR_Disable:1; 205 /// 206 /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving 207 /// for initiator internal errors (default); clear to enable. 208 /// 209 UINT32 InternalMCERR_Disable:1; 210 /// 211 /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver 212 /// (default); clear to enable driver. 213 /// 214 UINT32 BINIT_DriverDisable:1; 215 UINT32 Reserved1:25; 216 UINT32 Reserved2:32; 217 } Bits; 218 /// 219 /// All bit fields as a 32-bit value 220 /// 221 UINT32 Uint32; 222 /// 223 /// All bit fields as a 64-bit value 224 /// 225 UINT64 Uint64; 226 } MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER; 227 228 229 /** 230 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of 231 this MSR varies according to the MODEL value in the CPUID version 232 information. The following bit field layout applies to Pentium 4 and Xeon 233 Processors with MODEL encoding equal or greater than 2. (R) The field 234 Indicates the current processor frequency configuration. 235 236 @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C) 237 @param EAX Lower 32-bits of MSR value. 238 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER. 239 @param EDX Upper 32-bits of MSR value. 240 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER. 241 242 <b>Example usage</b> 243 @code 244 MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr; 245 246 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID); 247 @endcode 248 @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM. 249 **/ 250 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C 251 252 /** 253 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID 254 **/ 255 typedef union { 256 /// 257 /// Individual bit fields 258 /// 259 struct { 260 UINT32 Reserved1:16; 261 /// 262 /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable 263 /// bus speed: *EncodingScalable Bus Speed* 264 /// 265 /// 000B 100 MHz (Model 2). 266 /// 000B 266 MHz (Model 3 or 4) 267 /// 001B 133 MHz 268 /// 010B 200 MHz 269 /// 011B 166 MHz 270 /// 100B 333 MHz (Model 6) 271 /// 272 /// 133.33 MHz should be utilized if performing calculation with System 273 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if 274 /// performing calculation with System Bus Speed when encoding is 011B. 275 /// 266.67 MHz should be utilized if performing calculation with System 276 /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33 277 /// MHz should be utilized if performing calculation with System Bus 278 /// Speed when encoding is 100B and model encoding = 6. All other values 279 /// are reserved. 280 /// 281 UINT32 ScalableBusSpeed:3; 282 UINT32 Reserved2:5; 283 /// 284 /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R) 285 /// The processor core clock frequency to system bus frequency ratio 286 /// observed at the de-assertion of the reset pin. 287 /// 288 UINT32 ClockRatio:8; 289 UINT32 Reserved3:32; 290 } Bits; 291 /// 292 /// All bit fields as a 32-bit value 293 /// 294 UINT32 Uint32; 295 /// 296 /// All bit fields as a 64-bit value 297 /// 298 UINT64 Uint64; 299 } MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER; 300 301 302 /** 303 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of 304 this MSR varies according to the MODEL value of the CPUID version 305 information. This bit field layout applies to Pentium 4 and Xeon Processors 306 with MODEL encoding less than 2. Indicates current processor frequency 307 configuration. 308 309 @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C) 310 @param EAX Lower 32-bits of MSR value. 311 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER. 312 @param EDX Upper 32-bits of MSR value. 313 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER. 314 315 <b>Example usage</b> 316 @code 317 MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr; 318 319 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1); 320 @endcode 321 @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM. 322 **/ 323 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C 324 325 /** 326 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 327 **/ 328 typedef union { 329 /// 330 /// Individual bit fields 331 /// 332 struct { 333 UINT32 Reserved1:21; 334 /// 335 /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable 336 /// bus speed: *Encoding* *Scalable Bus Speed* 337 /// 338 /// 000B 100 MHz All others values reserved. 339 /// 340 UINT32 ScalableBusSpeed:3; 341 UINT32 Reserved2:8; 342 UINT32 Reserved3:32; 343 } Bits; 344 /// 345 /// All bit fields as a 32-bit value 346 /// 347 UINT32 Uint32; 348 /// 349 /// All bit fields as a 64-bit value 350 /// 351 UINT64 Uint64; 352 } MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER; 353 354 355 /** 356 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section 357 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 358 state at time of machine check error. When in non-64-bit modes at the time 359 of the error, bits 63-32 do not contain valid data. 360 361 @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180) 362 @param EAX Lower 32-bits of MSR value. 363 @param EDX Upper 32-bits of MSR value. 364 365 <b>Example usage</b> 366 @code 367 UINT64 Msr; 368 369 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX); 370 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr); 371 @endcode 372 @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM. 373 **/ 374 #define MSR_PENTIUM_4_MCG_RAX 0x00000180 375 376 377 /** 378 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section 379 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 380 state at time of machine check error. When in non-64-bit modes at the time 381 of the error, bits 63-32 do not contain valid data. 382 383 @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181) 384 @param EAX Lower 32-bits of MSR value. 385 @param EDX Upper 32-bits of MSR value. 386 387 <b>Example usage</b> 388 @code 389 UINT64 Msr; 390 391 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX); 392 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr); 393 @endcode 394 @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM. 395 **/ 396 #define MSR_PENTIUM_4_MCG_RBX 0x00000181 397 398 399 /** 400 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section 401 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 402 state at time of machine check error. When in non-64-bit modes at the time 403 of the error, bits 63-32 do not contain valid data. 404 405 @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182) 406 @param EAX Lower 32-bits of MSR value. 407 @param EDX Upper 32-bits of MSR value. 408 409 <b>Example usage</b> 410 @code 411 UINT64 Msr; 412 413 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX); 414 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr); 415 @endcode 416 @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM. 417 **/ 418 #define MSR_PENTIUM_4_MCG_RCX 0x00000182 419 420 421 /** 422 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section 423 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 424 state at time of machine check error. When in non-64-bit modes at the time 425 of the error, bits 63-32 do not contain valid data. 426 427 @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183) 428 @param EAX Lower 32-bits of MSR value. 429 @param EDX Upper 32-bits of MSR value. 430 431 <b>Example usage</b> 432 @code 433 UINT64 Msr; 434 435 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX); 436 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr); 437 @endcode 438 @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM. 439 **/ 440 #define MSR_PENTIUM_4_MCG_RDX 0x00000183 441 442 443 /** 444 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section 445 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 446 state at time of machine check error. When in non-64-bit modes at the time 447 of the error, bits 63-32 do not contain valid data. 448 449 @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184) 450 @param EAX Lower 32-bits of MSR value. 451 @param EDX Upper 32-bits of MSR value. 452 453 <b>Example usage</b> 454 @code 455 UINT64 Msr; 456 457 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI); 458 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr); 459 @endcode 460 @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM. 461 **/ 462 #define MSR_PENTIUM_4_MCG_RSI 0x00000184 463 464 465 /** 466 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section 467 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 468 state at time of machine check error. When in non-64-bit modes at the time 469 of the error, bits 63-32 do not contain valid data. 470 471 @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185) 472 @param EAX Lower 32-bits of MSR value. 473 @param EDX Upper 32-bits of MSR value. 474 475 <b>Example usage</b> 476 @code 477 UINT64 Msr; 478 479 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI); 480 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr); 481 @endcode 482 @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM. 483 **/ 484 #define MSR_PENTIUM_4_MCG_RDI 0x00000185 485 486 487 /** 488 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section 489 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 490 state at time of machine check error. When in non-64-bit modes at the time 491 of the error, bits 63-32 do not contain valid data. 492 493 @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186) 494 @param EAX Lower 32-bits of MSR value. 495 @param EDX Upper 32-bits of MSR value. 496 497 <b>Example usage</b> 498 @code 499 UINT64 Msr; 500 501 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP); 502 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr); 503 @endcode 504 @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM. 505 **/ 506 #define MSR_PENTIUM_4_MCG_RBP 0x00000186 507 508 509 /** 510 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section 511 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 512 state at time of machine check error. When in non-64-bit modes at the time 513 of the error, bits 63-32 do not contain valid data. 514 515 @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187) 516 @param EAX Lower 32-bits of MSR value. 517 @param EDX Upper 32-bits of MSR value. 518 519 <b>Example usage</b> 520 @code 521 UINT64 Msr; 522 523 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP); 524 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr); 525 @endcode 526 @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM. 527 **/ 528 #define MSR_PENTIUM_4_MCG_RSP 0x00000187 529 530 531 /** 532 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section 533 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 534 state at time of machine check error. When in non-64-bit modes at the time 535 of the error, bits 63-32 do not contain valid data. 536 537 @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188) 538 @param EAX Lower 32-bits of MSR value. 539 @param EDX Upper 32-bits of MSR value. 540 541 <b>Example usage</b> 542 @code 543 UINT64 Msr; 544 545 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS); 546 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr); 547 @endcode 548 @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM. 549 **/ 550 #define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188 551 552 553 /** 554 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section 555 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register 556 state at time of machine check error. When in non-64-bit modes at the time 557 of the error, bits 63-32 do not contain valid data. 558 559 @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189) 560 @param EAX Lower 32-bits of MSR value. 561 @param EDX Upper 32-bits of MSR value. 562 563 <b>Example usage</b> 564 @code 565 UINT64 Msr; 566 567 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP); 568 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr); 569 @endcode 570 @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM. 571 **/ 572 #define MSR_PENTIUM_4_MCG_RIP 0x00000189 573 574 575 /** 576 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6, 577 "IA32_MCG Extended Machine Check State MSRs.". 578 579 @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A) 580 @param EAX Lower 32-bits of MSR value. 581 Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER. 582 @param EDX Upper 32-bits of MSR value. 583 Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER. 584 585 <b>Example usage</b> 586 @code 587 MSR_PENTIUM_4_MCG_MISC_REGISTER Msr; 588 589 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC); 590 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64); 591 @endcode 592 @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM. 593 **/ 594 #define MSR_PENTIUM_4_MCG_MISC 0x0000018A 595 596 /** 597 MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC 598 **/ 599 typedef union { 600 /// 601 /// Individual bit fields 602 /// 603 struct { 604 /// 605 /// [Bit 0] DS When set, the bit indicates that a page assist or page 606 /// fault occurred during DS normal operation. The processors response is 607 /// to shut down. The bit is used as an aid for debugging DS handling 608 /// code. It is the responsibility of the user (BIOS or operating system) 609 /// to clear this bit for normal operation. 610 /// 611 UINT32 DS:1; 612 UINT32 Reserved1:31; 613 UINT32 Reserved2:32; 614 } Bits; 615 /// 616 /// All bit fields as a 32-bit value 617 /// 618 UINT32 Uint32; 619 /// 620 /// All bit fields as a 64-bit value 621 /// 622 UINT64 Uint64; 623 } MSR_PENTIUM_4_MCG_MISC_REGISTER; 624 625 626 /** 627 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG 628 Extended Machine Check State MSRs.". Registers R8-15 (and the associated 629 state-save MSRs) exist only in Intel 64 processors. These registers contain 630 valid information only when the processor is operating in 64-bit mode at the 631 time of the error. 632 633 @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190) 634 @param EAX Lower 32-bits of MSR value. 635 @param EDX Upper 32-bits of MSR value. 636 637 <b>Example usage</b> 638 @code 639 UINT64 Msr; 640 641 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8); 642 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr); 643 @endcode 644 @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM. 645 **/ 646 #define MSR_PENTIUM_4_MCG_R8 0x00000190 647 648 649 /** 650 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6, 651 "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the 652 associated state-save MSRs) exist only in Intel 64 processors. These 653 registers contain valid information only when the processor is operating in 654 64-bit mode at the time of the error. 655 656 @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191) 657 @param EAX Lower 32-bits of MSR value. 658 @param EDX Upper 32-bits of MSR value. 659 660 <b>Example usage</b> 661 @code 662 UINT64 Msr; 663 664 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9); 665 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr); 666 @endcode 667 @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM. 668 **/ 669 #define MSR_PENTIUM_4_MCG_R9 0x00000191 670 671 672 /** 673 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG 674 Extended Machine Check State MSRs.". Registers R8-15 (and the associated 675 state-save MSRs) exist only in Intel 64 processors. These registers contain 676 valid information only when the processor is operating in 64-bit mode at the 677 time of the error. 678 679 @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192) 680 @param EAX Lower 32-bits of MSR value. 681 @param EDX Upper 32-bits of MSR value. 682 683 <b>Example usage</b> 684 @code 685 UINT64 Msr; 686 687 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10); 688 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr); 689 @endcode 690 @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM. 691 **/ 692 #define MSR_PENTIUM_4_MCG_R10 0x00000192 693 694 695 /** 696 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG 697 Extended Machine Check State MSRs.". Registers R8-15 (and the associated 698 state-save MSRs) exist only in Intel 64 processors. These registers contain 699 valid information only when the processor is operating in 64-bit mode at the 700 time of the error. 701 702 @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193) 703 @param EAX Lower 32-bits of MSR value. 704 @param EDX Upper 32-bits of MSR value. 705 706 <b>Example usage</b> 707 @code 708 UINT64 Msr; 709 710 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11); 711 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr); 712 @endcode 713 @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM. 714 **/ 715 #define MSR_PENTIUM_4_MCG_R11 0x00000193 716 717 718 /** 719 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG 720 Extended Machine Check State MSRs.". Registers R8-15 (and the associated 721 state-save MSRs) exist only in Intel 64 processors. These registers contain 722 valid information only when the processor is operating in 64-bit mode at the 723 time of the error. 724 725 @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194) 726 @param EAX Lower 32-bits of MSR value. 727 @param EDX Upper 32-bits of MSR value. 728 729 <b>Example usage</b> 730 @code 731 UINT64 Msr; 732 733 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12); 734 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr); 735 @endcode 736 @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM. 737 **/ 738 #define MSR_PENTIUM_4_MCG_R12 0x00000194 739 740 741 /** 742 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG 743 Extended Machine Check State MSRs.". Registers R8-15 (and the associated 744 state-save MSRs) exist only in Intel 64 processors. These registers contain 745 valid information only when the processor is operating in 64-bit mode at the 746 time of the error. 747 748 @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195) 749 @param EAX Lower 32-bits of MSR value. 750 @param EDX Upper 32-bits of MSR value. 751 752 <b>Example usage</b> 753 @code 754 UINT64 Msr; 755 756 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13); 757 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr); 758 @endcode 759 @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM. 760 **/ 761 #define MSR_PENTIUM_4_MCG_R13 0x00000195 762 763 764 /** 765 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG 766 Extended Machine Check State MSRs.". Registers R8-15 (and the associated 767 state-save MSRs) exist only in Intel 64 processors. These registers contain 768 valid information only when the processor is operating in 64-bit mode at the 769 time of the error. 770 771 @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196) 772 @param EAX Lower 32-bits of MSR value. 773 @param EDX Upper 32-bits of MSR value. 774 775 <b>Example usage</b> 776 @code 777 UINT64 Msr; 778 779 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14); 780 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr); 781 @endcode 782 @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM. 783 **/ 784 #define MSR_PENTIUM_4_MCG_R14 0x00000196 785 786 787 /** 788 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG 789 Extended Machine Check State MSRs.". Registers R8-15 (and the associated 790 state-save MSRs) exist only in Intel 64 processors. These registers contain 791 valid information only when the processor is operating in 64-bit mode at the 792 time of the error. 793 794 @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197) 795 @param EAX Lower 32-bits of MSR value. 796 @param EDX Upper 32-bits of MSR value. 797 798 <b>Example usage</b> 799 @code 800 UINT64 Msr; 801 802 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15); 803 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr); 804 @endcode 805 @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM. 806 **/ 807 #define MSR_PENTIUM_4_MCG_R15 0x00000197 808 809 810 /** 811 Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors: 812 When read, specifies the value of the target TM2 transition last written. 813 When set, it sets the next target value for TM2 transition. 4, 6. Shared. 814 For Family F, Model 4 and Model 6 processors: When read, specifies the value 815 of the target TM2 transition last written. Writes may cause #GP exceptions. 816 817 @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D) 818 @param EAX Lower 32-bits of MSR value. 819 @param EDX Upper 32-bits of MSR value. 820 821 <b>Example usage</b> 822 @code 823 UINT64 Msr; 824 825 Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL); 826 AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr); 827 @endcode 828 @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. 829 **/ 830 #define MSR_PENTIUM_4_THERM2_CTL 0x0000019D 831 832 833 /** 834 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W). 835 836 @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0) 837 @param EAX Lower 32-bits of MSR value. 838 Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER. 839 @param EDX Upper 32-bits of MSR value. 840 Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER. 841 842 <b>Example usage</b> 843 @code 844 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr; 845 846 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE); 847 AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64); 848 @endcode 849 @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. 850 **/ 851 #define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0 852 853 /** 854 MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE 855 **/ 856 typedef union { 857 /// 858 /// Individual bit fields 859 /// 860 struct { 861 /// 862 /// [Bit 0] Fast-Strings Enable. See Table 35-2. 863 /// 864 UINT32 FastStrings:1; 865 UINT32 Reserved1:1; 866 /// 867 /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable. 868 /// 869 UINT32 FPU:1; 870 /// 871 /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal 872 /// Monitor," and see Table 35-2. 873 /// 874 UINT32 TM1:1; 875 /// 876 /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception 877 /// to be issued instead of a split-lock cycle. Operating systems that set 878 /// this bit must align system structures to avoid split-lock scenarios. 879 /// When the bit is clear (default), normal split-locks are issued to the 880 /// bus. 881 /// This debug feature is specific to the Pentium 4 processor. 882 /// 883 UINT32 SplitLockDisable:1; 884 UINT32 Reserved2:1; 885 /// 886 /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level 887 /// cache is disabled; when clear (default) the third-level cache is 888 /// enabled. This flag is reserved for processors that do not have a 889 /// third-level cache. Note that the bit controls only the third-level 890 /// cache; and only if overall caching is enabled through the CD flag of 891 /// control register CR0, the page-level cache controls, and/or the MTRRs. 892 /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.". 893 /// 894 UINT32 ThirdLevelCacheDisable:1; 895 /// 896 /// [Bit 7] Performance Monitoring Available (R) See Table 35-2. 897 /// 898 UINT32 PerformanceMonitoring:1; 899 /// 900 /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is 901 /// suppressed during a Split Lock access. When clear (default), LOCK is 902 /// not suppressed. 903 /// 904 UINT32 SuppressLockEnable:1; 905 /// 906 /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue. 907 /// When clear (default), enables the prefetch queue. 908 /// 909 UINT32 PrefetchQueueDisable:1; 910 /// 911 /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt 912 /// reporting through the FERR# pin is enabled; when clear, this interrupt 913 /// reporting function is disabled. 914 /// When this flag is set and the processor is in the stop-clock state 915 /// (STPCLK# is asserted), asserting the FERR# pin signals to the 916 /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI, 917 /// SMI#, or RESET#) is pending and that the processor should return to 918 /// normal operation to handle the interrupt. This flag does not affect 919 /// the normal operation of the FERR# pin (to indicate an unmasked 920 /// floatingpoint error) when the STPCLK# pin is not asserted. 921 /// 922 UINT32 FERR:1; 923 /// 924 /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See 925 /// Table 35-2. When set, the processor does not support branch trace 926 /// storage (BTS); when clear, BTS is supported. 927 /// 928 UINT32 BTS:1; 929 /// 930 /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable 931 /// (R) See Table 35-2. When set, the processor does not support processor 932 /// event-based sampling (PEBS); when clear, PEBS is supported. 933 /// 934 UINT32 PEBS:1; 935 /// 936 /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal 937 /// sensor indicates that the die temperature is at the predetermined 938 /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce 939 /// the bus to core ratio and voltage according to the value last written 940 /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the 941 /// processor does not change the VID signals or the bus to core ratio 942 /// when the processor enters a thermal managed state. If the TM2 feature 943 /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then 944 /// this feature is not supported and BIOS must not alter the contents of 945 /// this bit location. The processor is operating out of spec if both this 946 /// bit and the TM1 bit are set to disabled states. 947 /// 948 UINT32 TM2:1; 949 UINT32 Reserved3:4; 950 /// 951 /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 35-2. 952 /// 953 UINT32 MONITOR:1; 954 /// 955 /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1, 956 /// the processor fetches the cache line of the 128-byte sector containing 957 /// currently required data. When set to 0, the processor fetches both 958 /// cache lines in the sector. 959 /// Single processor platforms should not set this bit. Server platforms 960 /// should set or clear this bit based on platform performance observed 961 /// in validation and testing. BIOS may contain a setup option that 962 /// controls the setting of this bit. 963 /// 964 UINT32 AdjacentCacheLinePrefetchDisable:1; 965 UINT32 Reserved4:2; 966 /// 967 /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 35-2. Setting 968 /// this can cause unexpected behavior to software that depends on the 969 /// availability of CPUID leaves greater than 3. 970 /// 971 UINT32 LimitCpuidMaxval:1; 972 /// 973 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2. 974 /// 975 UINT32 xTPR_Message_Disable:1; 976 /// 977 /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache 978 /// is placed in shared mode; when clear (default), the cache is placed in 979 /// adaptive mode. This bit is only enabled for IA-32 processors that 980 /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data 981 /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are 982 /// identical, data in L1 is shared across logical processors. Otherwise, 983 /// L1 is not shared and cache use is competitive. If the Context ID 984 /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1, 985 /// the ability to switch modes is not supported. BIOS must not alter the 986 /// contents of IA32_MISC_ENABLE[24]. 987 /// 988 UINT32 L1DataCacheContextMode:1; 989 UINT32 Reserved5:7; 990 UINT32 Reserved6:2; 991 /// 992 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2. 993 /// 994 UINT32 XD:1; 995 UINT32 Reserved7:29; 996 } Bits; 997 /// 998 /// All bit fields as a 64-bit value 999 /// 1000 UINT64 Uint64; 1001 } MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER; 1002 1003 1004 /** 1005 3, 4, 6. Shared. Platform Feature Requirements (R). 1006 1007 @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1) 1008 @param EAX Lower 32-bits of MSR value. 1009 Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER. 1010 @param EDX Upper 32-bits of MSR value. 1011 Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER. 1012 1013 <b>Example usage</b> 1014 @code 1015 MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr; 1016 1017 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV); 1018 @endcode 1019 @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM. 1020 **/ 1021 #define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1 1022 1023 /** 1024 MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV 1025 **/ 1026 typedef union { 1027 /// 1028 /// Individual bit fields 1029 /// 1030 struct { 1031 UINT32 Reserved1:18; 1032 /// 1033 /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor 1034 /// has specific platform requirements. The details of the platform 1035 /// requirements are listed in the respective data sheets of the processor. 1036 /// 1037 UINT32 PLATFORM:1; 1038 UINT32 Reserved2:13; 1039 UINT32 Reserved3:32; 1040 } Bits; 1041 /// 1042 /// All bit fields as a 32-bit value 1043 /// 1044 UINT32 Uint32; 1045 /// 1046 /// All bit fields as a 64-bit value 1047 /// 1048 UINT64 Uint64; 1049 } MSR_PENTIUM_4_PLATFORM_BRV_REGISTER; 1050 1051 1052 /** 1053 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains 1054 a pointer to the last branch instruction that the processor executed prior 1055 to the last exception that was generated or the last interrupt that was 1056 handled. See Section 17.11.3, "Last Exception Records.". Unique. From Linear 1057 IP Linear address of the last branch instruction (If IA32e mode is active). 1058 From Linear IP Linear address of the last branch instruction. Reserved. 1059 1060 @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7) 1061 @param EAX Lower 32-bits of MSR value. 1062 @param EDX Upper 32-bits of MSR value. 1063 1064 <b>Example usage</b> 1065 @code 1066 UINT64 Msr; 1067 1068 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP); 1069 @endcode 1070 @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. 1071 **/ 1072 #define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7 1073 1074 1075 /** 1076 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area 1077 contains a pointer to the target of the last branch instruction that the 1078 processor executed prior to the last exception that was generated or the 1079 last interrupt that was handled. See Section 17.11.3, "Last Exception 1080 Records.". Unique. From Linear IP Linear address of the target of the last 1081 branch instruction (If IA-32e mode is active). From Linear IP Linear address 1082 of the target of the last branch instruction. Reserved. 1083 1084 @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8) 1085 @param EAX Lower 32-bits of MSR value. 1086 @param EDX Upper 32-bits of MSR value. 1087 1088 <b>Example usage</b> 1089 @code 1090 UINT64 Msr; 1091 1092 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP); 1093 @endcode 1094 @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. 1095 **/ 1096 #define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8 1097 1098 1099 /** 1100 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug 1101 features are used. Bit definitions are discussed in the referenced section. 1102 See Section 17.11.1, "MSR_DEBUGCTLA MSR.". 1103 1104 @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9) 1105 @param EAX Lower 32-bits of MSR value. 1106 @param EDX Upper 32-bits of MSR value. 1107 1108 <b>Example usage</b> 1109 @code 1110 UINT64 Msr; 1111 1112 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA); 1113 AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr); 1114 @endcode 1115 @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM. 1116 **/ 1117 #define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9 1118 1119 1120 /** 1121 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an 1122 index (0-3 or 0-15) that points to the top of the last branch record stack 1123 (that is, that points the index of the MSR containing the most recent branch 1124 record). See Section 17.11.2, "LBR Stack for Processors Based on Intel 1125 NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH. 1126 1127 @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA) 1128 @param EAX Lower 32-bits of MSR value. 1129 @param EDX Upper 32-bits of MSR value. 1130 1131 <b>Example usage</b> 1132 @code 1133 UINT64 Msr; 1134 1135 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS); 1136 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr); 1137 @endcode 1138 @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. 1139 **/ 1140 #define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA 1141 1142 1143 /** 1144 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record 1145 registers on the last branch record stack. It contains pointers to the 1146 source and destination instruction for one of the last four branches, 1147 exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through 1148 MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 1149 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See 1150 Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording 1151 for Processors based on Skylake Microarchitecture.". 1152 1153 @param ECX MSR_PENTIUM_4_LASTBRANCH_n 1154 @param EAX Lower 32-bits of MSR value. 1155 @param EDX Upper 32-bits of MSR value. 1156 1157 <b>Example usage</b> 1158 @code 1159 UINT64 Msr; 1160 1161 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0); 1162 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr); 1163 @endcode 1164 @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. 1165 MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. 1166 MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. 1167 MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. 1168 @{ 1169 **/ 1170 #define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB 1171 #define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC 1172 #define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD 1173 #define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE 1174 /// @} 1175 1176 1177 /** 1178 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.". 1179 1180 @param ECX MSR_PENTIUM_4_BPU_COUNTERn 1181 @param EAX Lower 32-bits of MSR value. 1182 @param EDX Upper 32-bits of MSR value. 1183 1184 <b>Example usage</b> 1185 @code 1186 UINT64 Msr; 1187 1188 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0); 1189 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr); 1190 @endcode 1191 @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM. 1192 MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM. 1193 MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM. 1194 MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM. 1195 @{ 1196 **/ 1197 #define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300 1198 #define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301 1199 #define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302 1200 #define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303 1201 /// @} 1202 1203 1204 /** 1205 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.". 1206 1207 @param ECX MSR_PENTIUM_4_MS_COUNTERn 1208 @param EAX Lower 32-bits of MSR value. 1209 @param EDX Upper 32-bits of MSR value. 1210 1211 <b>Example usage</b> 1212 @code 1213 UINT64 Msr; 1214 1215 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0); 1216 AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr); 1217 @endcode 1218 @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM. 1219 MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM. 1220 MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM. 1221 MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM. 1222 @{ 1223 **/ 1224 #define MSR_PENTIUM_4_MS_COUNTER0 0x00000304 1225 #define MSR_PENTIUM_4_MS_COUNTER1 0x00000305 1226 #define MSR_PENTIUM_4_MS_COUNTER2 0x00000306 1227 #define MSR_PENTIUM_4_MS_COUNTER3 0x00000307 1228 /// @} 1229 1230 1231 /** 1232 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.". 1233 1234 @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308) 1235 @param EAX Lower 32-bits of MSR value. 1236 @param EDX Upper 32-bits of MSR value. 1237 1238 <b>Example usage</b> 1239 @code 1240 UINT64 Msr; 1241 1242 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0); 1243 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr); 1244 @endcode 1245 @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM. 1246 MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM. 1247 MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM. 1248 MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM. 1249 @{ 1250 **/ 1251 #define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308 1252 #define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309 1253 #define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A 1254 #define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B 1255 /// @} 1256 1257 1258 /** 1259 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.". 1260 1261 @param ECX MSR_PENTIUM_4_IQ_COUNTERn 1262 @param EAX Lower 32-bits of MSR value. 1263 @param EDX Upper 32-bits of MSR value. 1264 1265 <b>Example usage</b> 1266 @code 1267 UINT64 Msr; 1268 1269 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0); 1270 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr); 1271 @endcode 1272 @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. 1273 MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. 1274 MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. 1275 MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. 1276 MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. 1277 MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM. 1278 @{ 1279 **/ 1280 #define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C 1281 #define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D 1282 #define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E 1283 #define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F 1284 #define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310 1285 #define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311 1286 /// @} 1287 1288 1289 /** 1290 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.". 1291 1292 @param ECX MSR_PENTIUM_4_BPU_CCCRn 1293 @param EAX Lower 32-bits of MSR value. 1294 @param EDX Upper 32-bits of MSR value. 1295 1296 <b>Example usage</b> 1297 @code 1298 UINT64 Msr; 1299 1300 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0); 1301 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr); 1302 @endcode 1303 @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM. 1304 MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM. 1305 MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM. 1306 MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM. 1307 @{ 1308 **/ 1309 #define MSR_PENTIUM_4_BPU_CCCR0 0x00000360 1310 #define MSR_PENTIUM_4_BPU_CCCR1 0x00000361 1311 #define MSR_PENTIUM_4_BPU_CCCR2 0x00000362 1312 #define MSR_PENTIUM_4_BPU_CCCR3 0x00000363 1313 /// @} 1314 1315 1316 /** 1317 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.". 1318 1319 @param ECX MSR_PENTIUM_4_MS_CCCRn 1320 @param EAX Lower 32-bits of MSR value. 1321 @param EDX Upper 32-bits of MSR value. 1322 1323 <b>Example usage</b> 1324 @code 1325 UINT64 Msr; 1326 1327 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0); 1328 AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr); 1329 @endcode 1330 @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM. 1331 MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM. 1332 MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM. 1333 MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM. 1334 @{ 1335 **/ 1336 #define MSR_PENTIUM_4_MS_CCCR0 0x00000364 1337 #define MSR_PENTIUM_4_MS_CCCR1 0x00000365 1338 #define MSR_PENTIUM_4_MS_CCCR2 0x00000366 1339 #define MSR_PENTIUM_4_MS_CCCR3 0x00000367 1340 /// @} 1341 1342 1343 /** 1344 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.". 1345 1346 @param ECX MSR_PENTIUM_4_FLAME_CCCRn 1347 @param EAX Lower 32-bits of MSR value. 1348 @param EDX Upper 32-bits of MSR value. 1349 1350 <b>Example usage</b> 1351 @code 1352 UINT64 Msr; 1353 1354 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0); 1355 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr); 1356 @endcode 1357 @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM. 1358 MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM. 1359 MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM. 1360 MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM. 1361 @{ 1362 **/ 1363 #define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368 1364 #define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369 1365 #define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A 1366 #define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B 1367 /// @} 1368 1369 1370 /** 1371 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.". 1372 1373 @param ECX MSR_PENTIUM_4_IQ_CCCRn 1374 @param EAX Lower 32-bits of MSR value. 1375 @param EDX Upper 32-bits of MSR value. 1376 1377 <b>Example usage</b> 1378 @code 1379 UINT64 Msr; 1380 1381 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0); 1382 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr); 1383 @endcode 1384 @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. 1385 MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. 1386 MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. 1387 MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. 1388 MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. 1389 MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM. 1390 @{ 1391 **/ 1392 #define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C 1393 #define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D 1394 #define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E 1395 #define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F 1396 #define MSR_PENTIUM_4_IQ_CCCR4 0x00000370 1397 #define MSR_PENTIUM_4_IQ_CCCR5 0x00000371 1398 /// @} 1399 1400 1401 /** 1402 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1403 1404 @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0) 1405 @param EAX Lower 32-bits of MSR value. 1406 @param EDX Upper 32-bits of MSR value. 1407 1408 <b>Example usage</b> 1409 @code 1410 UINT64 Msr; 1411 1412 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0); 1413 AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr); 1414 @endcode 1415 @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM. 1416 **/ 1417 #define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0 1418 1419 1420 /** 1421 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1422 1423 @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1) 1424 @param EAX Lower 32-bits of MSR value. 1425 @param EDX Upper 32-bits of MSR value. 1426 1427 <b>Example usage</b> 1428 @code 1429 UINT64 Msr; 1430 1431 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1); 1432 AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr); 1433 @endcode 1434 @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM. 1435 **/ 1436 #define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1 1437 1438 1439 /** 1440 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1441 1442 @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2) 1443 @param EAX Lower 32-bits of MSR value. 1444 @param EDX Upper 32-bits of MSR value. 1445 1446 <b>Example usage</b> 1447 @code 1448 UINT64 Msr; 1449 1450 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0); 1451 AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr); 1452 @endcode 1453 @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM. 1454 **/ 1455 #define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2 1456 1457 1458 /** 1459 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1460 1461 @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3) 1462 @param EAX Lower 32-bits of MSR value. 1463 @param EDX Upper 32-bits of MSR value. 1464 1465 <b>Example usage</b> 1466 @code 1467 UINT64 Msr; 1468 1469 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1); 1470 AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr); 1471 @endcode 1472 @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM. 1473 **/ 1474 #define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3 1475 1476 1477 /** 1478 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1479 1480 @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4) 1481 @param EAX Lower 32-bits of MSR value. 1482 @param EDX Upper 32-bits of MSR value. 1483 1484 <b>Example usage</b> 1485 @code 1486 UINT64 Msr; 1487 1488 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0); 1489 AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr); 1490 @endcode 1491 @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM. 1492 **/ 1493 #define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4 1494 1495 1496 /** 1497 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1498 1499 @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5) 1500 @param EAX Lower 32-bits of MSR value. 1501 @param EDX Upper 32-bits of MSR value. 1502 1503 <b>Example usage</b> 1504 @code 1505 UINT64 Msr; 1506 1507 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1); 1508 AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr); 1509 @endcode 1510 @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM. 1511 **/ 1512 #define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5 1513 1514 1515 /** 1516 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1517 1518 @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6) 1519 @param EAX Lower 32-bits of MSR value. 1520 @param EDX Upper 32-bits of MSR value. 1521 1522 <b>Example usage</b> 1523 @code 1524 UINT64 Msr; 1525 1526 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0); 1527 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr); 1528 @endcode 1529 @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM. 1530 **/ 1531 #define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6 1532 1533 1534 /** 1535 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1536 1537 @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7) 1538 @param EAX Lower 32-bits of MSR value. 1539 @param EDX Upper 32-bits of MSR value. 1540 1541 <b>Example usage</b> 1542 @code 1543 UINT64 Msr; 1544 1545 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1); 1546 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr); 1547 @endcode 1548 @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM. 1549 **/ 1550 #define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7 1551 1552 1553 /** 1554 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1555 1556 @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8) 1557 @param EAX Lower 32-bits of MSR value. 1558 @param EDX Upper 32-bits of MSR value. 1559 1560 <b>Example usage</b> 1561 @code 1562 UINT64 Msr; 1563 1564 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0); 1565 AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr); 1566 @endcode 1567 @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM. 1568 **/ 1569 #define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8 1570 1571 1572 /** 1573 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1574 1575 @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9) 1576 @param EAX Lower 32-bits of MSR value. 1577 @param EDX Upper 32-bits of MSR value. 1578 1579 <b>Example usage</b> 1580 @code 1581 UINT64 Msr; 1582 1583 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1); 1584 AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr); 1585 @endcode 1586 @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM. 1587 **/ 1588 #define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9 1589 1590 1591 /** 1592 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1593 1594 @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA) 1595 @param EAX Lower 32-bits of MSR value. 1596 @param EDX Upper 32-bits of MSR value. 1597 1598 <b>Example usage</b> 1599 @code 1600 UINT64 Msr; 1601 1602 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0); 1603 AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr); 1604 @endcode 1605 @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM. 1606 **/ 1607 #define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA 1608 1609 1610 /** 1611 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1612 1613 @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB) 1614 @param EAX Lower 32-bits of MSR value. 1615 @param EDX Upper 32-bits of MSR value. 1616 1617 <b>Example usage</b> 1618 @code 1619 UINT64 Msr; 1620 1621 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1); 1622 AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr); 1623 @endcode 1624 @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM. 1625 **/ 1626 #define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB 1627 1628 1629 /** 1630 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1631 1632 @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC) 1633 @param EAX Lower 32-bits of MSR value. 1634 @param EDX Upper 32-bits of MSR value. 1635 1636 <b>Example usage</b> 1637 @code 1638 UINT64 Msr; 1639 1640 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0); 1641 AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr); 1642 @endcode 1643 @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM. 1644 **/ 1645 #define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC 1646 1647 1648 /** 1649 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1650 1651 @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD) 1652 @param EAX Lower 32-bits of MSR value. 1653 @param EDX Upper 32-bits of MSR value. 1654 1655 <b>Example usage</b> 1656 @code 1657 UINT64 Msr; 1658 1659 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1); 1660 AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr); 1661 @endcode 1662 @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM. 1663 **/ 1664 #define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD 1665 1666 1667 /** 1668 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1669 1670 @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE) 1671 @param EAX Lower 32-bits of MSR value. 1672 @param EDX Upper 32-bits of MSR value. 1673 1674 <b>Example usage</b> 1675 @code 1676 UINT64 Msr; 1677 1678 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0); 1679 AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr); 1680 @endcode 1681 @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM. 1682 **/ 1683 #define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE 1684 1685 1686 /** 1687 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1688 1689 @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF) 1690 @param EAX Lower 32-bits of MSR value. 1691 @param EDX Upper 32-bits of MSR value. 1692 1693 <b>Example usage</b> 1694 @code 1695 UINT64 Msr; 1696 1697 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1); 1698 AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr); 1699 @endcode 1700 @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM. 1701 **/ 1702 #define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF 1703 1704 1705 /** 1706 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1707 1708 @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0) 1709 @param EAX Lower 32-bits of MSR value. 1710 @param EDX Upper 32-bits of MSR value. 1711 1712 <b>Example usage</b> 1713 @code 1714 UINT64 Msr; 1715 1716 Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0); 1717 AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr); 1718 @endcode 1719 @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM. 1720 **/ 1721 #define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0 1722 1723 1724 /** 1725 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1726 1727 @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1) 1728 @param EAX Lower 32-bits of MSR value. 1729 @param EDX Upper 32-bits of MSR value. 1730 1731 <b>Example usage</b> 1732 @code 1733 UINT64 Msr; 1734 1735 Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1); 1736 AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr); 1737 @endcode 1738 @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM. 1739 **/ 1740 #define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1 1741 1742 1743 /** 1744 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1745 1746 @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2) 1747 @param EAX Lower 32-bits of MSR value. 1748 @param EDX Upper 32-bits of MSR value. 1749 1750 <b>Example usage</b> 1751 @code 1752 UINT64 Msr; 1753 1754 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0); 1755 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr); 1756 @endcode 1757 @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM. 1758 **/ 1759 #define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2 1760 1761 1762 /** 1763 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1764 1765 @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3) 1766 @param EAX Lower 32-bits of MSR value. 1767 @param EDX Upper 32-bits of MSR value. 1768 1769 <b>Example usage</b> 1770 @code 1771 UINT64 Msr; 1772 1773 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1); 1774 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr); 1775 @endcode 1776 @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM. 1777 **/ 1778 #define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3 1779 1780 1781 /** 1782 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1783 1784 @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4) 1785 @param EAX Lower 32-bits of MSR value. 1786 @param EDX Upper 32-bits of MSR value. 1787 1788 <b>Example usage</b> 1789 @code 1790 UINT64 Msr; 1791 1792 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0); 1793 AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr); 1794 @endcode 1795 @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM. 1796 **/ 1797 #define MSR_PENTIUM_4_IS_ESCR0 0x000003B4 1798 1799 1800 /** 1801 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1802 1803 @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5) 1804 @param EAX Lower 32-bits of MSR value. 1805 @param EDX Upper 32-bits of MSR value. 1806 1807 <b>Example usage</b> 1808 @code 1809 UINT64 Msr; 1810 1811 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1); 1812 AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr); 1813 @endcode 1814 @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM. 1815 **/ 1816 #define MSR_PENTIUM_4_IS_ESCR1 0x000003B5 1817 1818 1819 /** 1820 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1821 1822 @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6) 1823 @param EAX Lower 32-bits of MSR value. 1824 @param EDX Upper 32-bits of MSR value. 1825 1826 <b>Example usage</b> 1827 @code 1828 UINT64 Msr; 1829 1830 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0); 1831 AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr); 1832 @endcode 1833 @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM. 1834 **/ 1835 #define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6 1836 1837 1838 /** 1839 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1840 1841 @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7) 1842 @param EAX Lower 32-bits of MSR value. 1843 @param EDX Upper 32-bits of MSR value. 1844 1845 <b>Example usage</b> 1846 @code 1847 UINT64 Msr; 1848 1849 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1); 1850 AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr); 1851 @endcode 1852 @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM. 1853 **/ 1854 #define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7 1855 1856 1857 /** 1858 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1859 1860 @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8) 1861 @param EAX Lower 32-bits of MSR value. 1862 @param EDX Upper 32-bits of MSR value. 1863 1864 <b>Example usage</b> 1865 @code 1866 UINT64 Msr; 1867 1868 Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0); 1869 AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr); 1870 @endcode 1871 @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM. 1872 **/ 1873 #define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8 1874 1875 1876 /** 1877 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1878 1879 @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9) 1880 @param EAX Lower 32-bits of MSR value. 1881 @param EDX Upper 32-bits of MSR value. 1882 1883 <b>Example usage</b> 1884 @code 1885 UINT64 Msr; 1886 1887 Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1); 1888 AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr); 1889 @endcode 1890 @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM. 1891 **/ 1892 #define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9 1893 1894 1895 /** 1896 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available 1897 on later processors. It is only available on processor family 0FH, models 1898 01H-02H. 1899 1900 @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA) 1901 @param EAX Lower 32-bits of MSR value. 1902 @param EDX Upper 32-bits of MSR value. 1903 1904 <b>Example usage</b> 1905 @code 1906 UINT64 Msr; 1907 1908 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0); 1909 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr); 1910 @endcode 1911 @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM. 1912 **/ 1913 #define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA 1914 1915 1916 /** 1917 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available 1918 on later processors. It is only available on processor family 0FH, models 1919 01H-02H. 1920 1921 @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB) 1922 @param EAX Lower 32-bits of MSR value. 1923 @param EDX Upper 32-bits of MSR value. 1924 1925 <b>Example usage</b> 1926 @code 1927 UINT64 Msr; 1928 1929 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1); 1930 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr); 1931 @endcode 1932 @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM. 1933 **/ 1934 #define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB 1935 1936 1937 /** 1938 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1939 1940 @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC) 1941 @param EAX Lower 32-bits of MSR value. 1942 @param EDX Upper 32-bits of MSR value. 1943 1944 <b>Example usage</b> 1945 @code 1946 UINT64 Msr; 1947 1948 Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0); 1949 AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr); 1950 @endcode 1951 @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM. 1952 **/ 1953 #define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC 1954 1955 1956 /** 1957 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1958 1959 @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD) 1960 @param EAX Lower 32-bits of MSR value. 1961 @param EDX Upper 32-bits of MSR value. 1962 1963 <b>Example usage</b> 1964 @code 1965 UINT64 Msr; 1966 1967 Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1); 1968 AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr); 1969 @endcode 1970 @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM. 1971 **/ 1972 #define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD 1973 1974 1975 /** 1976 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1977 1978 @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE) 1979 @param EAX Lower 32-bits of MSR value. 1980 @param EDX Upper 32-bits of MSR value. 1981 1982 <b>Example usage</b> 1983 @code 1984 UINT64 Msr; 1985 1986 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0); 1987 AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr); 1988 @endcode 1989 @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM. 1990 **/ 1991 #define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE 1992 1993 1994 /** 1995 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 1996 1997 @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0) 1998 @param EAX Lower 32-bits of MSR value. 1999 @param EDX Upper 32-bits of MSR value. 2000 2001 <b>Example usage</b> 2002 @code 2003 UINT64 Msr; 2004 2005 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0); 2006 AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr); 2007 @endcode 2008 @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM. 2009 **/ 2010 #define MSR_PENTIUM_4_MS_ESCR0 0x000003C0 2011 2012 2013 /** 2014 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2015 2016 @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1) 2017 @param EAX Lower 32-bits of MSR value. 2018 @param EDX Upper 32-bits of MSR value. 2019 2020 <b>Example usage</b> 2021 @code 2022 UINT64 Msr; 2023 2024 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1); 2025 AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr); 2026 @endcode 2027 @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM. 2028 **/ 2029 #define MSR_PENTIUM_4_MS_ESCR1 0x000003C1 2030 2031 2032 /** 2033 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2034 2035 @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2) 2036 @param EAX Lower 32-bits of MSR value. 2037 @param EDX Upper 32-bits of MSR value. 2038 2039 <b>Example usage</b> 2040 @code 2041 UINT64 Msr; 2042 2043 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0); 2044 AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr); 2045 @endcode 2046 @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM. 2047 **/ 2048 #define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2 2049 2050 2051 /** 2052 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2053 2054 @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3) 2055 @param EAX Lower 32-bits of MSR value. 2056 @param EDX Upper 32-bits of MSR value. 2057 2058 <b>Example usage</b> 2059 @code 2060 UINT64 Msr; 2061 2062 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1); 2063 AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr); 2064 @endcode 2065 @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM. 2066 **/ 2067 #define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3 2068 2069 2070 /** 2071 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2072 2073 @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4) 2074 @param EAX Lower 32-bits of MSR value. 2075 @param EDX Upper 32-bits of MSR value. 2076 2077 <b>Example usage</b> 2078 @code 2079 UINT64 Msr; 2080 2081 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0); 2082 AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr); 2083 @endcode 2084 @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM. 2085 **/ 2086 #define MSR_PENTIUM_4_TC_ESCR0 0x000003C4 2087 2088 2089 /** 2090 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2091 2092 @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5) 2093 @param EAX Lower 32-bits of MSR value. 2094 @param EDX Upper 32-bits of MSR value. 2095 2096 <b>Example usage</b> 2097 @code 2098 UINT64 Msr; 2099 2100 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1); 2101 AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr); 2102 @endcode 2103 @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM. 2104 **/ 2105 #define MSR_PENTIUM_4_TC_ESCR1 0x000003C5 2106 2107 2108 /** 2109 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2110 2111 @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8) 2112 @param EAX Lower 32-bits of MSR value. 2113 @param EDX Upper 32-bits of MSR value. 2114 2115 <b>Example usage</b> 2116 @code 2117 UINT64 Msr; 2118 2119 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0); 2120 AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr); 2121 @endcode 2122 @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM. 2123 **/ 2124 #define MSR_PENTIUM_4_IX_ESCR0 0x000003C8 2125 2126 2127 /** 2128 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2129 2130 @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9) 2131 @param EAX Lower 32-bits of MSR value. 2132 @param EDX Upper 32-bits of MSR value. 2133 2134 <b>Example usage</b> 2135 @code 2136 UINT64 Msr; 2137 2138 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1); 2139 AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr); 2140 @endcode 2141 @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM. 2142 **/ 2143 #define MSR_PENTIUM_4_IX_ESCR1 0x000003C9 2144 2145 2146 /** 2147 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2148 2149 @param ECX MSR_PENTIUM_4_ALF_ESCRn 2150 @param EAX Lower 32-bits of MSR value. 2151 @param EDX Upper 32-bits of MSR value. 2152 2153 <b>Example usage</b> 2154 @code 2155 UINT64 Msr; 2156 2157 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0); 2158 AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr); 2159 @endcode 2160 @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. 2161 MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. 2162 MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. 2163 MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. 2164 MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. 2165 MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM. 2166 @{ 2167 **/ 2168 #define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA 2169 #define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB 2170 #define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC 2171 #define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD 2172 #define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0 2173 #define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1 2174 /// @} 2175 2176 2177 /** 2178 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.". 2179 2180 @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0) 2181 @param EAX Lower 32-bits of MSR value. 2182 @param EDX Upper 32-bits of MSR value. 2183 2184 <b>Example usage</b> 2185 @code 2186 UINT64 Msr; 2187 2188 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT); 2189 AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr); 2190 @endcode 2191 @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM. 2192 **/ 2193 #define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0 2194 2195 2196 /** 2197 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W) 2198 Controls the enabling of processor event sampling and replay tagging. 2199 2200 @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1) 2201 @param EAX Lower 32-bits of MSR value. 2202 Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER. 2203 @param EDX Upper 32-bits of MSR value. 2204 Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER. 2205 2206 <b>Example usage</b> 2207 @code 2208 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr; 2209 2210 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE); 2211 AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64); 2212 @endcode 2213 @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. 2214 **/ 2215 #define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1 2216 2217 /** 2218 MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE 2219 **/ 2220 typedef union { 2221 /// 2222 /// Individual bit fields 2223 /// 2224 struct { 2225 /// 2226 /// [Bits 12:0] See Table 19-33. 2227 /// 2228 UINT32 EventNum:13; 2229 UINT32 Reserved1:11; 2230 /// 2231 /// [Bit 24] UOP Tag Enables replay tagging when set. 2232 /// 2233 UINT32 UOP:1; 2234 /// 2235 /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical 2236 /// processor when set; disables PEBS when clear (default). See Section 2237 /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target 2238 /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors 2239 /// that do not support Intel HyperThreading Technology. 2240 /// 2241 UINT32 ENABLE_PEBS_MY_THR:1; 2242 /// 2243 /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical 2244 /// processor when set; disables PEBS when clear (default). See Section 2245 /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target 2246 /// logical processor. This bit is reserved for IA-32 processors that do 2247 /// not support Intel Hyper-Threading Technology. 2248 /// 2249 UINT32 ENABLE_PEBS_OTH_THR:1; 2250 UINT32 Reserved2:5; 2251 UINT32 Reserved3:32; 2252 } Bits; 2253 /// 2254 /// All bit fields as a 32-bit value 2255 /// 2256 UINT32 Uint32; 2257 /// 2258 /// All bit fields as a 64-bit value 2259 /// 2260 UINT64 Uint64; 2261 } MSR_PENTIUM_4_PEBS_ENABLE_REGISTER; 2262 2263 2264 /** 2265 0, 1, 2, 3, 4, 6. Shared. See Table 19-33. 2266 2267 @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2) 2268 @param EAX Lower 32-bits of MSR value. 2269 @param EDX Upper 32-bits of MSR value. 2270 2271 <b>Example usage</b> 2272 @code 2273 UINT64 Msr; 2274 2275 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT); 2276 AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr); 2277 @endcode 2278 @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM. 2279 **/ 2280 #define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2 2281 2282 2283 /** 2284 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch 2285 record registers on the last branch record stack (680H-68FH). This part of 2286 the stack contains pointers to the source instruction for one of the last 16 2287 branches, exceptions, or interrupts taken by the processor. The MSRs at 2288 680H-68FH, 6C0H-6CfH are not available in processor releases before family 2289 0FH, model 03H. These MSRs replace MSRs previously located at 2290 1DBH-1DEH.which performed the same function for early releases. See Section 2291 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording for 2292 Processors based on Skylake Microarchitecture.". 2293 2294 @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP 2295 @param EAX Lower 32-bits of MSR value. 2296 @param EDX Upper 32-bits of MSR value. 2297 2298 <b>Example usage</b> 2299 @code 2300 UINT64 Msr; 2301 2302 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP); 2303 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr); 2304 @endcode 2305 @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. 2306 MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. 2307 MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. 2308 MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. 2309 MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. 2310 MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. 2311 MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. 2312 MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. 2313 MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. 2314 MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. 2315 MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. 2316 MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. 2317 MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. 2318 MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. 2319 MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. 2320 MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. 2321 @{ 2322 **/ 2323 #define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680 2324 #define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681 2325 #define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682 2326 #define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683 2327 #define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684 2328 #define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685 2329 #define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686 2330 #define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687 2331 #define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688 2332 #define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689 2333 #define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A 2334 #define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B 2335 #define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C 2336 #define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D 2337 #define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E 2338 #define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F 2339 /// @} 2340 2341 2342 /** 2343 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch 2344 record registers on the last branch record stack (6C0H-6CFH). This part of 2345 the stack contains pointers to the destination instruction for one of the 2346 last 16 branches, exceptions, or interrupts that the processor took. See 2347 Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording 2348 for Processors based on Skylake Microarchitecture.". 2349 2350 @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP 2351 @param EAX Lower 32-bits of MSR value. 2352 @param EDX Upper 32-bits of MSR value. 2353 2354 <b>Example usage</b> 2355 @code 2356 UINT64 Msr; 2357 2358 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP); 2359 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr); 2360 @endcode 2361 @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. 2362 MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. 2363 MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. 2364 MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. 2365 MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. 2366 MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. 2367 MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. 2368 MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. 2369 MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. 2370 MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. 2371 MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. 2372 MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. 2373 MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. 2374 MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. 2375 MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. 2376 MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. 2377 @{ 2378 **/ 2379 #define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0 2380 #define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1 2381 #define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2 2382 #define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3 2383 #define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4 2384 #define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5 2385 #define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6 2386 #define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7 2387 #define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8 2388 #define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9 2389 #define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA 2390 #define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB 2391 #define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC 2392 #define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD 2393 #define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE 2394 #define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF 2395 /// @} 2396 2397 2398 /** 2399 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See 2400 Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP 2401 with Up to 8-MByte L3 Cache.". 2402 2403 @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC) 2404 @param EAX Lower 32-bits of MSR value. 2405 @param EDX Upper 32-bits of MSR value. 2406 2407 <b>Example usage</b> 2408 @code 2409 UINT64 Msr; 2410 2411 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0); 2412 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr); 2413 @endcode 2414 @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM. 2415 **/ 2416 #define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC 2417 2418 2419 /** 2420 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W). 2421 2422 @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD) 2423 @param EAX Lower 32-bits of MSR value. 2424 @param EDX Upper 32-bits of MSR value. 2425 2426 <b>Example usage</b> 2427 @code 2428 UINT64 Msr; 2429 2430 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1); 2431 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr); 2432 @endcode 2433 @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM. 2434 **/ 2435 #define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD 2436 2437 2438 /** 2439 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See 2440 Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP 2441 with Up to 8-MByte L3 Cache.". 2442 2443 @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE) 2444 @param EAX Lower 32-bits of MSR value. 2445 @param EDX Upper 32-bits of MSR value. 2446 2447 <b>Example usage</b> 2448 @code 2449 UINT64 Msr; 2450 2451 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0); 2452 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr); 2453 @endcode 2454 @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM. 2455 **/ 2456 #define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE 2457 2458 2459 /** 2460 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W). 2461 2462 @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF) 2463 @param EAX Lower 32-bits of MSR value. 2464 @param EDX Upper 32-bits of MSR value. 2465 2466 <b>Example usage</b> 2467 @code 2468 UINT64 Msr; 2469 2470 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1); 2471 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr); 2472 @endcode 2473 @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM. 2474 **/ 2475 #define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF 2476 2477 2478 /** 2479 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See 2480 Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP 2481 with Up to 8-MByte L3 Cache" for details. 2482 2483 @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0) 2484 @param EAX Lower 32-bits of MSR value. 2485 @param EDX Upper 32-bits of MSR value. 2486 2487 <b>Example usage</b> 2488 @code 2489 UINT64 Msr; 2490 2491 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0); 2492 AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr); 2493 @endcode 2494 @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM. 2495 **/ 2496 #define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0 2497 2498 2499 /** 2500 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W). 2501 2502 @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1) 2503 @param EAX Lower 32-bits of MSR value. 2504 @param EDX Upper 32-bits of MSR value. 2505 2506 <b>Example usage</b> 2507 @code 2508 UINT64 Msr; 2509 2510 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1); 2511 AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr); 2512 @endcode 2513 @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM. 2514 **/ 2515 #define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1 2516 2517 2518 /** 2519 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.21, 2520 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte 2521 L3 Cache" for details. 2522 2523 @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2) 2524 @param EAX Lower 32-bits of MSR value. 2525 @param EDX Upper 32-bits of MSR value. 2526 2527 <b>Example usage</b> 2528 @code 2529 UINT64 Msr; 2530 2531 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6); 2532 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr); 2533 @endcode 2534 @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM. 2535 **/ 2536 #define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2 2537 2538 2539 /** 2540 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.21, 2541 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte 2542 L3 Cache.". 2543 2544 @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3) 2545 @param EAX Lower 32-bits of MSR value. 2546 @param EDX Upper 32-bits of MSR value. 2547 2548 <b>Example usage</b> 2549 @code 2550 UINT64 Msr; 2551 2552 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7); 2553 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr); 2554 @endcode 2555 @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM. 2556 **/ 2557 #define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3 2558 2559 2560 /** 2561 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.21, 2562 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte 2563 L3 Cache.". 2564 2565 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC) 2566 @param EAX Lower 32-bits of MSR value. 2567 @param EDX Upper 32-bits of MSR value. 2568 2569 <b>Example usage</b> 2570 @code 2571 UINT64 Msr; 2572 2573 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0); 2574 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr); 2575 @endcode 2576 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM. 2577 **/ 2578 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC 2579 2580 2581 /** 2582 6. Shared. GBUSQ Event Control and Counter Register (R/W). 2583 2584 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD) 2585 @param EAX Lower 32-bits of MSR value. 2586 @param EDX Upper 32-bits of MSR value. 2587 2588 <b>Example usage</b> 2589 @code 2590 UINT64 Msr; 2591 2592 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1); 2593 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr); 2594 @endcode 2595 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM. 2596 **/ 2597 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD 2598 2599 2600 /** 2601 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section 2602 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 2603 8-MByte L3 Cache.". 2604 2605 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE) 2606 @param EAX Lower 32-bits of MSR value. 2607 @param EDX Upper 32-bits of MSR value. 2608 2609 <b>Example usage</b> 2610 @code 2611 UINT64 Msr; 2612 2613 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2); 2614 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr); 2615 @endcode 2616 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM. 2617 **/ 2618 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE 2619 2620 2621 /** 2622 6. Shared. GSNPQ Event Control and Counter Register (R/W). 2623 2624 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF) 2625 @param EAX Lower 32-bits of MSR value. 2626 @param EDX Upper 32-bits of MSR value. 2627 2628 <b>Example usage</b> 2629 @code 2630 UINT64 Msr; 2631 2632 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3); 2633 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr); 2634 @endcode 2635 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM. 2636 **/ 2637 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF 2638 2639 2640 /** 2641 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.21, 2642 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte 2643 L3 Cache" for details. 2644 2645 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0) 2646 @param EAX Lower 32-bits of MSR value. 2647 @param EDX Upper 32-bits of MSR value. 2648 2649 <b>Example usage</b> 2650 @code 2651 UINT64 Msr; 2652 2653 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4); 2654 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr); 2655 @endcode 2656 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM. 2657 **/ 2658 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0 2659 2660 2661 /** 2662 6. Shared. FSB Event Control and Counter Register (R/W). 2663 2664 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1) 2665 @param EAX Lower 32-bits of MSR value. 2666 @param EDX Upper 32-bits of MSR value. 2667 2668 <b>Example usage</b> 2669 @code 2670 UINT64 Msr; 2671 2672 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5); 2673 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr); 2674 @endcode 2675 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM. 2676 **/ 2677 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1 2678 2679 2680 /** 2681 6. Shared. FSB Event Control and Counter Register (R/W). 2682 2683 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2) 2684 @param EAX Lower 32-bits of MSR value. 2685 @param EDX Upper 32-bits of MSR value. 2686 2687 <b>Example usage</b> 2688 @code 2689 UINT64 Msr; 2690 2691 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6); 2692 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr); 2693 @endcode 2694 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM. 2695 **/ 2696 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2 2697 2698 2699 /** 2700 6. Shared. FSB Event Control and Counter Register (R/W). 2701 2702 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3) 2703 @param EAX Lower 32-bits of MSR value. 2704 @param EDX Upper 32-bits of MSR value. 2705 2706 <b>Example usage</b> 2707 @code 2708 UINT64 Msr; 2709 2710 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7); 2711 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr); 2712 @endcode 2713 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM. 2714 **/ 2715 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3 2716 2717 #endif 2718
