1 /** @file 2 MSR Definitions for Intel(R) Xeon(R) Processor E7 Family. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8. 21 22 **/ 23 24 #ifndef __XEON_E7_MSR_H__ 25 #define __XEON_E7_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP 31 handler to handle unsuccessful read of this MSR. 32 33 @param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C) 34 @param EAX Lower 32-bits of MSR value. 35 Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER. 36 @param EDX Upper 32-bits of MSR value. 37 Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER. 38 39 <b>Example usage</b> 40 @code 41 MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr; 42 43 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG); 44 AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64); 45 @endcode 46 @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM. 47 **/ 48 #define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C 49 50 /** 51 MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG 52 **/ 53 typedef union { 54 /// 55 /// Individual bit fields 56 /// 57 struct { 58 /// 59 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this 60 /// MSR, the configuration of AES instruction set availability is as 61 /// follows: 11b: AES instructions are not available until next RESET. 62 /// otherwise, AES instructions are available. Note, AES instruction set 63 /// is not available if read is unsuccessful. If the configuration is not 64 /// 01b, AES instruction can be mis-configured if a privileged agent 65 /// unintentionally writes 11b. 66 /// 67 UINT32 AESConfiguration:2; 68 UINT32 Reserved1:30; 69 UINT32 Reserved2:32; 70 } Bits; 71 /// 72 /// All bit fields as a 32-bit value 73 /// 74 UINT32 Uint32; 75 /// 76 /// All bit fields as a 64-bit value 77 /// 78 UINT64 Uint64; 79 } MSR_XEON_E7_FEATURE_CONFIG_REGISTER; 80 81 82 /** 83 Thread. Offcore Response Event Select Register (R/W). 84 85 @param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7) 86 @param EAX Lower 32-bits of MSR value. 87 @param EDX Upper 32-bits of MSR value. 88 89 <b>Example usage</b> 90 @code 91 UINT64 Msr; 92 93 Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1); 94 AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr); 95 @endcode 96 @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM. 97 **/ 98 #define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7 99 100 101 /** 102 Package. Reserved Attempt to read/write will cause #UD. 103 104 @param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD) 105 @param EAX Lower 32-bits of MSR value. 106 @param EDX Upper 32-bits of MSR value. 107 108 <b>Example usage</b> 109 @code 110 UINT64 Msr; 111 112 Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT); 113 AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr); 114 @endcode 115 @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 116 **/ 117 #define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD 118 119 120 /** 121 Package. Uncore C-box 8 perfmon local box control MSR. 122 123 @param ECX MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40) 124 @param EAX Lower 32-bits of MSR value. 125 @param EDX Upper 32-bits of MSR value. 126 127 <b>Example usage</b> 128 @code 129 UINT64 Msr; 130 131 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL); 132 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr); 133 @endcode 134 @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM. 135 **/ 136 #define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40 137 138 139 /** 140 Package. Uncore C-box 8 perfmon local box status MSR. 141 142 @param ECX MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41) 143 @param EAX Lower 32-bits of MSR value. 144 @param EDX Upper 32-bits of MSR value. 145 146 <b>Example usage</b> 147 @code 148 UINT64 Msr; 149 150 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS); 151 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr); 152 @endcode 153 @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM. 154 **/ 155 #define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41 156 157 158 /** 159 Package. Uncore C-box 8 perfmon local box overflow control MSR. 160 161 @param ECX MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42) 162 @param EAX Lower 32-bits of MSR value. 163 @param EDX Upper 32-bits of MSR value. 164 165 <b>Example usage</b> 166 @code 167 UINT64 Msr; 168 169 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL); 170 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr); 171 @endcode 172 @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM. 173 **/ 174 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42 175 176 177 /** 178 Package. Uncore C-box 8 perfmon event select MSR. 179 180 @param ECX MSR_XEON_E7_C8_PMON_EVNT_SELn 181 @param EAX Lower 32-bits of MSR value. 182 @param EDX Upper 32-bits of MSR value. 183 184 <b>Example usage</b> 185 @code 186 UINT64 Msr; 187 188 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0); 189 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr); 190 @endcode 191 @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM. 192 MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM. 193 MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM. 194 MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM. 195 MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM. 196 MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM. 197 @{ 198 **/ 199 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50 200 #define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52 201 #define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54 202 #define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56 203 #define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58 204 #define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A 205 /// @} 206 207 208 /** 209 Package. Uncore C-box 8 perfmon counter MSR. 210 211 @param ECX MSR_XEON_E7_C8_PMON_CTRn 212 @param EAX Lower 32-bits of MSR value. 213 @param EDX Upper 32-bits of MSR value. 214 215 <b>Example usage</b> 216 @code 217 UINT64 Msr; 218 219 Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0); 220 AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr); 221 @endcode 222 @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM. 223 MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM. 224 MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM. 225 MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM. 226 MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM. 227 MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM. 228 @{ 229 **/ 230 #define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51 231 #define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53 232 #define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55 233 #define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57 234 #define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59 235 #define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B 236 /// @} 237 238 239 /** 240 Package. Uncore C-box 9 perfmon local box control MSR. 241 242 @param ECX MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0) 243 @param EAX Lower 32-bits of MSR value. 244 @param EDX Upper 32-bits of MSR value. 245 246 <b>Example usage</b> 247 @code 248 UINT64 Msr; 249 250 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL); 251 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr); 252 @endcode 253 @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM. 254 **/ 255 #define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0 256 257 258 /** 259 Package. Uncore C-box 9 perfmon local box status MSR. 260 261 @param ECX MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1) 262 @param EAX Lower 32-bits of MSR value. 263 @param EDX Upper 32-bits of MSR value. 264 265 <b>Example usage</b> 266 @code 267 UINT64 Msr; 268 269 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS); 270 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr); 271 @endcode 272 @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM. 273 **/ 274 #define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1 275 276 277 /** 278 Package. Uncore C-box 9 perfmon local box overflow control MSR. 279 280 @param ECX MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2) 281 @param EAX Lower 32-bits of MSR value. 282 @param EDX Upper 32-bits of MSR value. 283 284 <b>Example usage</b> 285 @code 286 UINT64 Msr; 287 288 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL); 289 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr); 290 @endcode 291 @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM. 292 **/ 293 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2 294 295 296 /** 297 Package. Uncore C-box 9 perfmon event select MSR. 298 299 @param ECX MSR_XEON_E7_C9_PMON_EVNT_SELn 300 @param EAX Lower 32-bits of MSR value. 301 @param EDX Upper 32-bits of MSR value. 302 303 <b>Example usage</b> 304 @code 305 UINT64 Msr; 306 307 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0); 308 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr); 309 @endcode 310 @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM. 311 MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM. 312 MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM. 313 MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM. 314 MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM. 315 MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM. 316 @{ 317 **/ 318 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0 319 #define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2 320 #define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4 321 #define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6 322 #define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8 323 #define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA 324 /// @} 325 326 327 /** 328 Package. Uncore C-box 9 perfmon counter MSR. 329 330 @param ECX MSR_XEON_E7_C9_PMON_CTRn 331 @param EAX Lower 32-bits of MSR value. 332 @param EDX Upper 32-bits of MSR value. 333 334 <b>Example usage</b> 335 @code 336 UINT64 Msr; 337 338 Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0); 339 AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr); 340 @endcode 341 @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM. 342 MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM. 343 MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM. 344 MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM. 345 MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM. 346 MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM. 347 @{ 348 **/ 349 #define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1 350 #define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3 351 #define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5 352 #define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7 353 #define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9 354 #define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB 355 /// @} 356 357 #endif 358
