1 /** @file 2 Multiplatform initialization. 3 4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR> 5 6 This program and the accompanying materials are licensed and made available under 8 the terms and conditions of the BSD License that accompanies this distribution. 10 The full text of the license may be found at 12 http://opensource.org/licenses/bsd-license.php. 14 16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 20 22 24 **/ 25 26 #include <MultiPlatformLib.h> 27 28 /** 29 Platform Type detection. Because the PEI globle variable 30 is in the flash, it could not change directly.So use 31 2 PPIs to distinguish the platform type. 32 33 @param FfsHeader Pointer to Firmware File System file header. 34 @param PeiServices General purpose services available to every PEIM. 35 36 @retval EFI_SUCCESS Memory initialization completed successfully. 37 @retval Others All other error conditions encountered result in an ASSERT. 38 39 **/ 40 EFI_STATUS 41 MultiPlatformInfoInit ( 42 IN CONST EFI_PEI_SERVICES **PeiServices, 43 IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob 44 ) 45 { 46 UINT32 PcieLength; 47 48 49 PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET); 50 51 PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET); 52 53 // 54 // Update ICH Type 55 // 56 // 57 // Device ID 58 // 59 PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET); 60 61 PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET); 62 63 // 64 //64MB 65 // 66 PcieLength = 0x04000000; 67 68 // 69 // Don't support BASE above 4GB currently. 70 // 71 PlatformInfoHob->PciData.PciExpressSize = PcieLength; 72 PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress); 73 74 PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN); 75 PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1); 76 77 PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE; 78 PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT; 79 PlatformInfoHob->CpuData.CpuAddressWidth = 36; 80 81 PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base; 82 PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1; 83 84 PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus; 85 86 // 87 // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base. 88 // 89 if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) { 90 PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base; 91 } else { 92 PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase; 93 } 94 PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm; 95 96 // 97 // Platform PCI MMIO Size in unit of 1MB. 98 // 99 PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20); 100 101 // 102 // Enable ICH IOAPIC 103 // 104 PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC; 105 106 DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n", 107 PlatformInfoHob->PlatformFlavor, 108 FlavorTablet, 109 FlavorMobile, 110 FlavorDesktop)); 111 112 // 113 // Get Platform Info and fill the Hob. 114 // 115 PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION; 116 117 // 118 // Get GPIO table 119 // 120 MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob); 121 122 // 123 // Program GPIO 124 // 125 MultiPlatformGpioProgram (PeiServices, PlatformInfoHob); 126 127 // 128 // Update OemId 129 // 130 InitializeBoardOemId (PeiServices, PlatformInfoHob); 131 InitializeBoardSsidSvid (PeiServices, PlatformInfoHob); 132 133 return EFI_SUCCESS; 134 } 135
