1 /*++ 2 3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR> 4 5 This program and the accompanying materials are licensed and made available under 7 the terms and conditions of the BSD License that accompanies this distribution. 9 The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php. 13 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 19 21 23 Module Name: 24 25 Configuration.h 26 27 Abstract: 28 29 Driver configuration include file 30 31 32 --*/ 33 34 #ifndef _CONFIGURATION_H 35 #define _CONFIGURATION_H 36 37 #define EFI_NON_DEVICE_CLASS 0x00 38 #define EFI_DISK_DEVICE_CLASS 0x01 39 #define EFI_VIDEO_DEVICE_CLASS 0x02 40 #define EFI_NETWORK_DEVICE_CLASS 0x04 41 #define EFI_INPUT_DEVICE_CLASS 0x08 42 #define EFI_ON_BOARD_DEVICE_CLASS 0x10 43 #define EFI_OTHER_DEVICE_CLASS 0x20 44 45 // 46 // Processor labels 47 // 48 #define PROCESSOR_HT_MODE 0x0100 49 #define PROCESSOR_FSB_MULTIPLIER 0x0101 50 #define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL 0x0211 51 52 // 53 // Memory labels 54 // 55 #define MEMORY_SLOT1_SPEED 0x0200 56 #define MEMORY_SLOT2_SPEED 0x0201 57 #define MEMORY_SLOT3_SPEED 0x0202 58 #define MEMORY_SLOT4_SPEED 0x0203 59 #define END_MEMORY_SLOT_SPEED 0x020F 60 #define PERFORMANCE_MEMORY_PROFILE_CONTROL 0x0210 61 #define UCLK_RATIO_CONTROL 0x0212 62 63 // 64 // Language label 65 // 66 #define FRONT_PAGE_ITEM_LANGUAGE 0x300 67 68 // 69 // Boot Labels 70 // 71 #define BOOT_DEVICE_PRIORITY_BEGIN 0x0400 72 #define BOOT_DEVICE_PRIORITY_END 0x0401 73 #define BOOT_OPTICAL_DEVICE_BEGIN 0x0410 74 #define BOOT_OPTICAL_DEVICE_END 0x0411 75 #define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420 76 #define BOOT_REMOVABLE_DEVICE_END 0x0421 77 #define BOOT_PXE_DEVICE_BEGIN 0x0430 78 #define BOOT_PXE_DEVICE_END 0x0431 79 #define BOOT_MENU_TYPE_BEGIN 0x0440 80 #define BOOT_MENU_TYPE_END 0x0441 81 #define BOOT_USB_DEVICE_BEGIN 0x0450 82 #define BOOT_USB_DEVICE_END 0x0451 83 #define BOOT_USB_FIRST_BEGIN 0x0460 84 #define BOOT_USB_FIRST_END 0x0461 85 #define BOOT_UEFI_BEGIN 0x0470 86 #define BOOT_UEFI_END 0x0471 87 #define BOOT_USB_UNAVAILABLE_BEGIN 0x0480 88 #define BOOT_USB_UNAVAILABLE_END 0x0481 89 #define BOOT_CD_UNAVAILABLE_BEGIN 0x0490 90 #define BOOT_CD_UNAVAILABLE_END 0x0491 91 #define BOOT_FDD_UNAVAILABLE_BEGIN 0x04A0 92 #define BOOT_FDD_UNAVAILABLE_END 0x04A1 93 #define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN 0x04B0 94 #define BOOT_DEVICE_PRIORITY_DEFAULT_END 0x04B1 95 #define BOOT_USB_OPT_LABEL_BEGIN 0x04C0 96 #define BOOT_USB_OPT_LABEL_END 0x04C1 97 98 #define VAR_EQ_ADMIN_NAME 0x0041 // A 99 #define VAR_EQ_ADMIN_DECIMAL_NAME L"65" 100 #define VAR_EQ_VIEW_ONLY_NAME 0x0042 // B 101 #define VAR_EQ_VIEW_ONLY_DECIMAL_NAME L"66" 102 #define VAR_EQ_CONFIG_MODE_NAME 0x0043 // C 103 #define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67" 104 #define VAR_EQ_CPU_EE_NAME 0x0045 // E 105 #define VAR_EQ_CPU_EE_DECIMAL_NAME L"69" 106 #define VAR_EQ_FLOPPY_MODE_NAME 0x0046 // F 107 #define VAR_EQ_FLOPPY_MODE_DECIMAL_NAME L"70" 108 #define VAR_EQ_HT_MODE_NAME 0x0048 // H 109 #define VAR_EQ_HT_MODE_DECIMAL_NAME L"72" 110 #define VAR_EQ_AHCI_MODE_NAME 0x0049 // I 111 #define VAR_EQ_AHCI_MODE_DECIMAL_NAME L"73" 112 #define VAR_EQ_CPU_LOCK_NAME 0x004C // L 113 #define VAR_EQ_CPU_LOCK_DECIMAL_NAME L"76" 114 #define VAR_EQ_NX_MODE_NAME 0x004E // N 115 #define VAR_EQ_NX_MODE_DECIMAL_NAME L"78" 116 #define VAR_EQ_RAID_MODE_NAME 0x0052 // R 117 #define VAR_EQ_RAID_MODE_DECIMAL_NAME L"82" 118 #define VAR_EQ_1394_MODE_NAME 0x0054 // T 119 #define VAR_EQ_1394_MODE_DECIMAL_NAME L"84" 120 #define VAR_EQ_USER_NAME 0x0055 // U 121 #define VAR_EQ_USER_DECIMAL_NAME L"85" 122 #define VAR_EQ_VIDEO_MODE_NAME 0x0056 // V 123 #define VAR_EQ_VIDEO_MODE_DECIMAL_NAME L"86" 124 #define VAR_EQ_LEGACY_FP_AUDIO_NAME 0x0057 // W 125 #define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87" 126 #define VAR_EQ_EM64T_CAPABLE_NAME 0x0058 // X 127 #define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88" 128 #define VAR_EQ_BOARD_FORMFACTOR_NAME 0x0059 // Y 129 #define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89" 130 #define VAR_EQ_UNCON_CPU_NAME 0x005B // ?? 131 #define VAR_EQ_UNCON_CPU_DECIMAL_NAME L"91" 132 #define VAR_EQ_VAR_HIDE_NAME 0x005C // ?? 133 #define VAR_EQ_VAR_HIDE_DECIMAL_NAME L"92" 134 #define VAR_EQ_ENERGY_LAKE_NAME 0x005D // ?? 135 #define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93" 136 #define VAR_EQ_TPM_MODE_NAME 0x005E // ^ 137 #define VAR_EQ_TPM_MODE_DECIMAL_NAME L"94" 138 #define VAR_EQ_DISCRETE_SATA_NAME 0x005F // ?? 139 #define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95" 140 #define VAR_EQ_ROEM_SKU_NAME 0x0060 // ?? 141 #define VAR_EQ_ROEM_SKU_DECIMAL_NAME L"96" 142 #define VAR_EQ_AMTSOL_MODE_NAME 0x0061 // ?? 143 #define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97" 144 #define VAR_EQ_NO_PEG_MODE_NAME 0x0062 // ?? 145 #define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98" 146 #define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063 // ?? 147 #define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99" 148 #define VAR_EQ_FLOPPY_HIDE_NAME 0x0064 // ?? 149 #define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100" 150 #define VAR_EQ_SERIAL_HIDE_NAME 0x0065 // ?? 151 #define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101" 152 #define VAR_EQ_GV3_CAPABLE_NAME 0x0066 // f 153 #define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102" 154 #define VAR_EQ_2_MEMORY_NAME 0x0067 // ?? 155 #define VAR_EQ_2_MEMORY_DECIMAL_NAME L"103" 156 #define VAR_EQ_2_SATA_NAME 0x0068 // ?? 157 #define VAR_EQ_2_SATA_DECIMAL_NAME L"104" 158 #define VAR_EQ_NEC_SKU_NAME 0x0069 // ?? 159 #define VAR_EQ_NEC_SKU_DECIMAL_NAME L"105" 160 #define VAR_EQ_AMT_MODE_NAME 0x006A // ?? 161 #define VAR_EQ_AMT_MODE_DECIMAL_NAME L"106" 162 #define VAR_EQ_LCLX_SKU_NAME 0x006B // ?? 163 #define VAR_EQ_LCLX_SKU_DECIMAL_NAME L"107" 164 #define VAR_EQ_VT_NAME 0x006C 165 #define VAR_EQ_VT_DECIMAL_NAME L"108" 166 #define VAR_EQ_LT_NAME 0x006D 167 #define VAR_EQ_LT_DECIMAL_NAME L"109" 168 #define VAR_EQ_ITK_BIOS_MOD_NAME 0x006E // ?? 169 #define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110" 170 #define VAR_EQ_HPET_NAME 0x006F 171 #define VAR_EQ_HPET_DECIMAL_NAME L"111" 172 #define VAR_EQ_ADMIN_INSTALLED_NAME 0x0070 // ?? 173 #define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME L"112" 174 #define VAR_EQ_USER_INSTALLED_NAME 0x0071 // ?? 175 #define VAR_EQ_USER_INSTALLED_DECIMAL_NAME L"113" 176 #define VAR_EQ_CPU_CMP_NAME 0x0072 177 #define VAR_EQ_CPU_CMP_DECIMAL_NAME L"114" 178 #define VAR_EQ_LAN_MAC_ADDR_NAME 0x0073 // ?? 179 #define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME L"115" 180 #define VAR_EQ_PARALLEL_HIDE_NAME 0x0074 // ?? 181 #define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116" 182 #define VAR_EQ_AFSC_SETUP_NAME 0x0075 183 #define VAR_EQ_AFSC_SETUP_DECIMAL_NAME L"117" 184 #define VAR_EQ_MINICARD_MODE_NAME 0x0076 // 185 #define VAR_EQ_MINICARD_MODE_DECIMAL_NAME L"118" 186 #define VAR_EQ_VIDEO_IGD_NAME 0x0077 // 187 #define VAR_EQ_VIDEO_IGD_DECIMAL_NAME L"119" 188 #define VAR_EQ_ALWAYS_ENABLE_LAN_NAME 0x0078 // 189 #define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME L"120" 190 #define VAR_EQ_LEGACY_FREE_NAME 0x0079 // 191 #define VAR_EQ_LEGACY_FREE_DECIMAL_NAME L"121" 192 #define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME 0x007A 193 #define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME L"122" 194 #define VAR_EQ_CPU_FSB_NAME 0x007B // 195 #define VAR_EQ_CPU_FSB_DECIMAL_NAME L"123" 196 #define VAR_EQ_SATA0_DEVICE_NAME 0x007C // 197 #define VAR_EQ_SATA0_DVICE_DECIMAL_NAME L"124" 198 #define VAR_EQ_SATA1_DEVICE_NAME 0x007D // 199 #define VAR_EQ_SATA1_DVICE_DECIMAL_NAME L"125" 200 #define VAR_EQ_SATA2_DEVICE_NAME 0x007E // 201 #define VAR_EQ_SATA2_DVICE_DECIMAL_NAME L"126" 202 #define VAR_EQ_SATA3_DEVICE_NAME 0x007F // 203 #define VAR_EQ_SATA3_DVICE_DECIMAL_NAME L"127" 204 #define VAR_EQ_SATA4_DEVICE_NAME 0x0080 // 205 #define VAR_EQ_SATA4_DVICE_DECIMAL_NAME L"128" 206 #define VAR_EQ_SATA5_DEVICE_NAME 0x0081 // 207 #define VAR_EQ_SATA5_DVICE_DECIMAL_NAME L"129" 208 #define VAR_EQ_TPM_STATUS_NAME 0x0082 // To indicate if TPM is enabled 209 #define VAR_EQ_TPM_STATUS_DECIMAL_NAME L"130" 210 #define VAR_EQ_HECETA6E_PECI_CPU_NAME 0x0083 211 #define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131" 212 #define VAR_EQ_USB_2_NAME 0x0084 // 213 #define VAR_EQ_USB_2_DECIMAL_NAME L"132" 214 #define VAR_EQ_RVP_NAME 0x0085 // 215 #define VAR_EQ_RVP_DECIMAL_NAME L"133" 216 #define VAR_EQ_ECIR_NAME 0x0086 217 #define VAR_EQ_ECIR_DECIMAL_NAME L"134" 218 #define VAR_EQ_WAKONS5KB_NAME 0x0087 219 #define VAR_EQ_WAKONS5KB_DECIMAL_NAME L"135" 220 #define VAR_EQ_HDAUDIOLINKBP_NAME 0x0088 221 #define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME L"136" 222 #define VAR_EQ_FINGERPRINT_NAME 0x0089 223 #define VAR_EQ_FINGERPRINT_DECIMAL_NAME L"137" 224 #define VAR_EQ_BLUETOOTH_NAME 0x008A 225 #define VAR_EQ_BLUETOOTH_DECIMAL_NAME L"138" 226 #define VAR_EQ_WLAN_NAME 0x008B 227 #define VAR_EQ_WLAN_DECIMAL_NAME L"139" 228 #define VAR_EQ_1_PATA_NAME 0x008C 229 #define VAR_EQ_1_PATA_DECIMAL_NAME L"140" 230 #define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME 0x008D 231 #define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME L"141" 232 #define VAR_EQ_TURBO_MODE_CAP_NAME 0x008E 233 #define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME L"142" 234 #define VAR_EQ_XE_MODE_CAP_NAME 0x008F 235 #define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME L"143" 236 #define VAR_EQ_NPI_QPI_VOLTAGE_NAME 0x0090 237 #define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144" 238 #define VAR_EQ_PRE_PROD_NON_XE_NAME 0x0091 239 #define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145" 240 #define VAR_EQ_2_C0_MEMORY_NAME 0x0092 // ?? 241 #define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME L"146" 242 #define VAR_EQ_LVDS_NAME 0x0093 243 #define VAR_EQ_LVDS_DECIMAL_NAME L"147" 244 #define VAR_EQ_USB_OPTION_SHOW_NAME 0x0094 245 #define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME L"148" 246 #define VAR_EQ_HDD_MASTER_INSTALLED_NAME 0x0095 247 #define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME L"149" 248 #define VAR_EQ_HDD_USER_INSTALLED_NAME 0x0096 249 #define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME L"150" 250 #define VAR_EQ_PS2_HIDE_NAME 0x0097 // ?? 251 #define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151" 252 #define VAR_EQ_VIDEO_SLOT_NAME 0x0098 253 #define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME L"152" 254 #define VAR_EQ_HDMI_SLOT_NAME 0x0099 255 #define VAR_EQ_HDMI_SLOT_DECIMAL_NAME L"153" 256 #define VAR_EQ_SERIAL2_HIDE_NAME 0x009a 257 #define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154" 258 259 260 #define VAR_EQ_LVDS_WARNING_HIDE_NAME 0x009e 261 #define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158" 262 263 264 #define VAR_EQ_MSATA_HIDE_NAME 0x009f 265 #define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159" 266 267 268 #define VAR_EQ_PCI_SLOT1_NAME 0x00a0 269 #define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160" 270 #define VAR_EQ_PCI_SLOT2_NAME 0x00a1 271 #define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161" 272 273 // 274 // Generic Form Ids 275 // 276 #define ROOT_FORM_ID 1 277 278 // 279 // Advance Page. Do not have to be sequential but have to be unique 280 // 281 #define CONFIGURATION_ROOT_FORM_ID 2 282 #define BOOT_CONFIGURATION_ID 3 283 #define ONBOARDDEVICE_CONFIGURATION_ID 4 284 #define DRIVE_CONFIGURATION_ID 5 285 #define FLOPPY_CONFIGURATION_ID 6 286 #define EVENT_LOG_CONFIGURATION_ID 7 287 #define VIDEO_CONFIGURATION_ID 8 288 #define USB_CONFIGURATION_ID 9 289 #define HARDWARE_MONITOR_CONFIGURATION_ID 10 290 #define VIEW_EVENT_LOG_CONFIGURATION_ID 11 291 #define MEMORY_OVERRIDE_ID 12 292 #define CHIPSET_CONFIGURATION_ID 13 293 #define BURN_IN_MODE_ID 14 294 #define PCI_EXPRESS_ID 15 295 #define MANAGEMENT_CONFIGURATION_ID 16 296 #define CPU_CONFIGURATION_ID 17 297 #define PCI_CONFIGURATION_ID 18 298 #define SECURITY_CONFIGURATION_ID 19 299 #define ZIP_CONFIGURATION_ID 20 300 #define AFSC_FAN_CONTROL_ID 21 301 #define VFR_FORMID_CSI 22 302 #define VFR_FORMID_MEMORY 23 303 #define VFR_FORMID_IOH 24 304 #define VFR_FORMID_CPU_CSI 25 305 #define VFR_FORMID_IOH_CONFIG 26 306 #define VFR_FORMID_VTD 27 307 #define VFR_FORMID_PCIE_P0 28 308 #define VFR_FORMID_PCIE_P1 29 309 #define VFR_FORMID_PCIE_P2 30 310 #define VFR_FORMID_PCIE_P3 31 311 #define VFR_FORMID_PCIE_P4 32 312 #define VFR_FORMID_PCIE_P5 33 313 #define VFR_FORMID_PCIE_P6 34 314 #define VFR_FORMID_PCIE_P7 35 315 #define VFR_FORMID_PCIE_P8 36 316 #define VFR_FORMID_PCIE_P9 37 317 #define VFR_FORMID_PCIE_P10 38 318 #define VFR_FID_SKT0 39 319 #define VFR_FID_IOH0 40 320 #define VFR_FID_IOH_DEV_HIDE 41 321 #define PROCESSOR_OVERRIDES_FORM_ID 42 322 #define BUS_OVERRIDES_FORM_ID 43 323 #define REF_OVERRIDES_FORM_ID 44 324 #define MEMORY_INFORMATION_ID 45 325 #define LVDS_WARNING_ID 46 326 #define LVDS_CONFIGURATION_ID 47 327 #define PCI_SLOT_CONFIGURATION_ID 48 328 #define HECETA_CONFIGURATION_ID 49 329 #define LVDS_EXPERT_CONFIGURATION_ID 50 330 #define PCI_SLOT_7_ID 51 331 #define PCI_SLOT_6_ID 52 332 #define PCI_SLOT_5_ID 53 333 #define PCI_SLOT_4_ID 54 334 #define PCI_SLOT_3_ID 55 335 #define PCI_SLOT_2_ID 56 336 #define PCI_SLOT_1_ID 57 337 #define BOOT_DISPLAY_ID 58 338 #define CPU_PWR_CONFIGURATION_ID 59 339 340 #define FSC_CONFIGURATION_ID 60 341 #define FSC_CPU_TEMPERATURE_FORM_ID 61 342 #define FSC_VTT_VOLTAGE_FORM_ID 62 343 #define FSC_FEATURES_CONTROL_ID 63 344 #define FSC_FAN_CONFIGURATION_ID 64 345 #define FSC_PROCESSOR_FAN_CONFIGURATION_ID 65 346 #define FSC_FRONT_FAN_CONFIGURATION_ID 66 347 #define FSC_REAR_FAN_CONFIGURATION_ID 67 348 #define FSC_AUX_FAN_CONFIGURATION_ID 68 349 #define FSC_12_VOLTAGE_FORM_ID 69 350 #define FSC_5_VOLTAGE_FORM_ID 70 351 #define FSC_3P3_VOLTAGE_FORM_ID 71 352 #define FSC_2P5_VOLTAGE_FORM_ID 72 353 #define FSC_VCC_VOLTAGE_FORM_ID 73 354 #define FSC_PCH_TEMPERATURE_FORM_ID 74 355 #define FSC_MEM_TEMPERATURE_FORM_ID 75 356 #define FSC_VR_TEMPERATURE_FORM_ID 76 357 #define FSC_3P3STANDBY_VOLTAGE_FORM_ID 77 358 #define FSC_5BACKUP_VOLTAGE_FORM_ID 78 359 #define ROOT_MAIN_FORM_ID 79 360 #define ROOT_BOOT_FORM_ID 80 361 #define ROOT_MAINTENANCE_ID 81 362 #define ROOT_POWER_FORM_ID 82 363 #define ROOT_SECURITY_FORM_ID 83 364 #define ROOT_PERFORMANCE_FORM_ID 84 365 #define ROOT_SYSTEM_SETUP_FORM_ID 85 366 367 #define ADDITIONAL_SYSTEM_INFO_FORM_ID 86 368 369 #define THERMAL_CONFIG_FORM_ID 87 370 371 #define PCI_SLOT_CONFIG_LABEL_ID_1 0x300A 372 #define PCI_SLOT_CONFIG_LABEL_ID_2 0x300B 373 #define PCI_SLOT_CONFIG_LABEL_ID_3 0x300C 374 #define PCI_SLOT_CONFIG_LABEL_ID_4 0x300D 375 #define PCI_SLOT_CONFIG_LABEL_ID_5 0x300E 376 #define PCI_SLOT_CONFIG_LABEL_ID_6 0x300F 377 #define PCI_SLOT_CONFIG_LABEL_ID_7 0x3010 378 #define PCI_SLOT_CONFIG_LABEL_ID_8 0x3011 379 380 // 381 // Advance Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique 382 // 383 #define CONFIGURATION_HARDWARE_CALLBACK_KEY 0x2000 384 #define ADVANCE_VIDEO_CALLBACK_KEY 0x2001 385 #define CONFIGURATION_FSC_CALLBACK_KEY 0x2002 386 #define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY 0x2003 387 #define CONFIGURATION_LVDS_CALLBACK_KEY 0x2004 388 #define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY 0x2005 389 #define ADVANCE_LVDS_CALLBACK_KEY 0x2010 390 391 // 392 // Main Callback Keys. Do not have to be sequential but have to be unique 393 // 394 #define MAIN_LANGUAGE_CALLBACK_KEY 0x3000 395 396 // 397 // Power Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique 398 // 399 #define POWER_HARDWARE_CALLBACK_KEY 0x4000 400 401 // 402 // Performance Callback Keys. Do not have to be sequential but have to be unique 403 // 404 #define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000 405 #define PERFORMANCE_CALLBACK_KEY 0x5001 406 #define BUS_OVERRIDES_CALLBACK_KEY 0x5002 407 #define MEMORY_CFG_CALLBACK_KEY 0x5003 408 #define PERFORMANCE_STATUS_CALLBACK_KEY 0x5004 409 #define MEMORY_RATIO_CALLBACK_KEY 0x5005 410 #define MEMORY_MODE_CALLBACK_KEY 0x5006 411 412 // 413 // Security Callback Keys. Do not have to be sequential but have to be unique 414 // 415 #define SECURITY_SUPERVISOR_CALLBACK_KEY 0x1000 416 #define SECURITY_USER_CALLBACK_KEY 0x1001 417 #define SECURITY_CLEAR_ALL_CALLBACK_KEY 0x1002 418 #define SECURITY_CLEAR_USER_CALLBACK_KEY 0x1004 419 #define SECURITY_RESET_AMT_CALLBACK_KEY 0x1008 420 #define SECURITY_CHANGE_VT_CALLBACK_KEY 0x1010 421 #define SECURITY_MASTER_HDD_CALLBACK_KEY 0x1020 422 #define SECURITY_USER_HDD_CALLBACK_KEY 0x1040 423 424 // 425 // Boot Callback Keys. Do not have to be sequential but have to be unique 426 // 427 #define BOOT_HYPERBOOT_CALLBACK_KEY 0x6003 428 #define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE 0x6004 429 #define BOOT_HYPERBOOT_CALLBACK_KEY_USB 0x6005 430 #define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006 431 432 // 433 // IDCC/Setup FSB Frequency Override Range 434 // 435 #define EFI_IDCC_FSB_MIN 133 436 #define EFI_IDCC_FSB_MAX 240 437 #define EFI_IDCC_FSB_STEP 1 438 439 // 440 // Reference voltage 441 // 442 #define EFI_REF_DAC_MIN 0 443 #define EFI_REF_DAC_MAX 255 444 #define EFI_GTLREF_DEF 170 445 #define EFI_DDRREF_DEF 128 446 #define EFI_DIMMREF_DEF 128 447 448 // 449 // Setup FSB Frequency Override Range 450 // 451 #define EFI_FSB_MIN 133 452 #define EFI_FSB_MAX 240 453 #define EFI_FSB_STEP 1 454 #define EFI_FSB_AUTOMATIC 0 455 #define EFI_FSB_MANUAL 1 456 #define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX - EFI_FSB_MIN)/EFI_FSB_STEP) + 1 457 #define FSB_FREQ_ENTRY_TYPE UINT16_TYPE 458 459 // 460 // Setup processor multiplier range 461 // 462 #define EFI_PROC_MULT_MIN 5 463 #define EFI_PROC_MULT_MAX 40 464 #define EFI_PROC_MULT_STEP 1 465 #define EFI_PROC_AUTOMATIC 0 466 #define EFI_PROC_MANUAL 1 467 #define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX - EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1 468 #define PROC_MULT_ENTRY_TYPE UINT8_TYPE 469 470 // 471 // PCI Express Definitions 472 // 473 #define EFI_PCIE_FREQ_DEF 0x0 474 475 #define PCIE_FREQ_ENTRY_TYPE UINT8_TYPE 476 #define PCIE_FREQ_ENTRY_7 0x7 477 #define PCIE_FREQ_ENTRY_6 0x6 478 #define PCIE_FREQ_ENTRY_5 0x5 479 #define PCIE_FREQ_ENTRY_4 0x4 480 #define PCIE_FREQ_ENTRY_3 0x3 481 #define PCIE_FREQ_ENTRY_2 0x2 482 #define PCIE_FREQ_ENTRY_1 0x1 483 #define PCIE_FREQ_ENTRY_0 0x0 484 485 #define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8 486 #define PCIE_FREQ_TRANSLATION_TABLE { PCIE_FREQ_ENTRY_0, \ 487 PCIE_FREQ_ENTRY_1, \ 488 PCIE_FREQ_ENTRY_2, \ 489 PCIE_FREQ_ENTRY_3, \ 490 PCIE_FREQ_ENTRY_4, \ 491 PCIE_FREQ_ENTRY_5, \ 492 PCIE_FREQ_ENTRY_6, \ 493 PCIE_FREQ_ENTRY_7 } 494 495 496 #define PCIE_FREQ_PRECISION 2 497 #define PCIE_FREQ_VALUE_7 10924 498 #define PCIE_FREQ_VALUE_6 10792 499 #define PCIE_FREQ_VALUE_5 10660 500 #define PCIE_FREQ_VALUE_4 10528 501 #define PCIE_FREQ_VALUE_3 10396 502 #define PCIE_FREQ_VALUE_2 10264 503 #define PCIE_FREQ_VALUE_1 10132 504 #define PCIE_FREQ_VALUE_0 10000 505 506 #define PCIE_FREQ_VALUES { PCIE_FREQ_VALUE_0, \ 507 PCIE_FREQ_VALUE_1, \ 508 PCIE_FREQ_VALUE_2, \ 509 PCIE_FREQ_VALUE_3, \ 510 PCIE_FREQ_VALUE_4, \ 511 PCIE_FREQ_VALUE_5, \ 512 PCIE_FREQ_VALUE_6, \ 513 PCIE_FREQ_VALUE_7 } 514 515 // 516 // Memory Frequency Definitions 517 // 518 #define MEMORY_REF_FREQ_ENTRY_DEF 0x08 519 520 #define MEMORY_REF_FREQ_ENTRY_TYPE UINT8_TYPE 521 #define MEMORY_REF_FREQ_ENTRY_3 0x04 522 #define MEMORY_REF_FREQ_ENTRY_2 0x00 523 #define MEMORY_REF_FREQ_ENTRY_1 0x02 524 #define MEMORY_REF_FREQ_ENTRY_0 0x01 525 526 #define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4 527 #define MEMORY_REF_FREQ_TRANSLATION_TABLE { MEMORY_REF_FREQ_ENTRY_0, \ 528 MEMORY_REF_FREQ_ENTRY_1, \ 529 MEMORY_REF_FREQ_ENTRY_2, \ 530 MEMORY_REF_FREQ_ENTRY_3 } 531 532 #define MEMORY_REF_FREQ_PRECISION 0 533 #define MEMORY_REF_FREQ_VALUE_3 333 534 #define MEMORY_REF_FREQ_VALUE_2 267 535 #define MEMORY_REF_FREQ_VALUE_1 200 536 #define MEMORY_REF_FREQ_VALUE_0 133 537 538 #define MEMORY_REF_FREQ_VALUES { MEMORY_REF_FREQ_VALUE_0, \ 539 MEMORY_REF_FREQ_VALUE_1, \ 540 MEMORY_REF_FREQ_VALUE_2, \ 541 MEMORY_REF_FREQ_VALUE_3 } 542 543 544 // 545 // Memory Reference Frequency Definitions 546 // 547 548 #define MEMORY_FREQ_ENTRY_TYPE UINT8_TYPE 549 #define MEMORY_FREQ_ENTRY_3 0x4 550 #define MEMORY_FREQ_ENTRY_2 0x3 551 #define MEMORY_FREQ_ENTRY_1 0x2 552 #define MEMORY_FREQ_ENTRY_0 0x1 553 554 #define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4 555 #define MEMORY_FREQ_TRANSLATION_TABLE { MEMORY_FREQ_ENTRY_0, \ 556 MEMORY_FREQ_ENTRY_1, \ 557 MEMORY_FREQ_ENTRY_2, \ 558 MEMORY_FREQ_ENTRY_3 } 559 560 561 #define MEMORY_FREQ_MULT_PRECISION 2 562 #define MEMORY_FREQ_MULT_333MHZ_VALUE_3 240 563 #define MEMORY_FREQ_MULT_333MHZ_VALUE_2 200 564 #define MEMORY_FREQ_MULT_333MHZ_VALUE_1 160 565 #define MEMORY_FREQ_MULT_333MHZ_VALUE_0 120 566 567 #define MEMORY_FREQ_MULT_266MHZ_VALUE_3 300 568 #define MEMORY_FREQ_MULT_266MHZ_VALUE_2 250 569 #define MEMORY_FREQ_MULT_266MHZ_VALUE_1 200 570 #define MEMORY_FREQ_MULT_266MHZ_VALUE_0 150 571 572 #define MEMORY_FREQ_MULT_200MHZ_VALUE_3 400 573 #define MEMORY_FREQ_MULT_200MHZ_VALUE_2 333 574 #define MEMORY_FREQ_MULT_200MHZ_VALUE_1 267 575 #define MEMORY_FREQ_MULT_200MHZ_VALUE_0 200 576 577 #define MEMORY_FREQ_MULT_133MHZ_VALUE_3 600 578 #define MEMORY_FREQ_MULT_133MHZ_VALUE_2 500 579 #define MEMORY_FREQ_MULT_133MHZ_VALUE_1 400 580 #define MEMORY_FREQ_MULT_133MHZ_VALUE_0 300 581 582 #define MEMORY_FREQ_MULT_333MHZ_VALUES { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \ 583 MEMORY_FREQ_MULT_333MHZ_VALUE_1, \ 584 MEMORY_FREQ_MULT_333MHZ_VALUE_2, \ 585 MEMORY_FREQ_MULT_333MHZ_VALUE_3 } 586 587 #define MEMORY_FREQ_MULT_266MHZ_VALUES { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \ 588 MEMORY_FREQ_MULT_266MHZ_VALUE_1, \ 589 MEMORY_FREQ_MULT_266MHZ_VALUE_2, \ 590 MEMORY_FREQ_MULT_266MHZ_VALUE_3 } 591 592 #define MEMORY_FREQ_MULT_200MHZ_VALUES { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \ 593 MEMORY_FREQ_MULT_200MHZ_VALUE_1, \ 594 MEMORY_FREQ_MULT_200MHZ_VALUE_2, \ 595 MEMORY_FREQ_MULT_200MHZ_VALUE_3 } 596 597 #define MEMORY_FREQ_MULT_133MHZ_VALUES { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \ 598 MEMORY_FREQ_MULT_133MHZ_VALUE_1, \ 599 MEMORY_FREQ_MULT_133MHZ_VALUE_2, \ 600 MEMORY_FREQ_MULT_133MHZ_VALUE_3 } 601 602 // 603 // CAS Memory Timing Definitions 604 // 605 606 #define MEMORY_TCL_ENTRY_TYPE UINT8_TYPE 607 #define MEMORY_TCL_ENTRY_3 0x2 608 #define MEMORY_TCL_ENTRY_2 0x1 609 #define MEMORY_TCL_ENTRY_1 0x0 610 #define MEMORY_TCL_ENTRY_0 0x3 611 612 #define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4 613 #define MEMORY_TCL_TRANSLATION_TABLE { MEMORY_TCL_ENTRY_0, \ 614 MEMORY_TCL_ENTRY_1, \ 615 MEMORY_TCL_ENTRY_2, \ 616 MEMORY_TCL_ENTRY_3 } 617 618 619 #define MEMORY_TCL_PRECISION 0 620 #define MEMORY_TCL_VALUE_3 3 621 #define MEMORY_TCL_VALUE_2 4 622 #define MEMORY_TCL_VALUE_1 5 623 #define MEMORY_TCL_VALUE_0 6 624 625 #define MEMORY_TCL_VALUES { MEMORY_TCL_VALUE_0, \ 626 MEMORY_TCL_VALUE_1, \ 627 MEMORY_TCL_VALUE_2, \ 628 MEMORY_TCL_VALUE_3 } 629 630 631 // 632 // TRCD Memory Timing Definitions 633 // 634 635 #define MEMORY_TRCD_ENTRY_TYPE UINT8_TYPE 636 #define MEMORY_TRCD_ENTRY_3 0x0 637 #define MEMORY_TRCD_ENTRY_2 0x1 638 #define MEMORY_TRCD_ENTRY_1 0x2 639 #define MEMORY_TRCD_ENTRY_0 0x3 640 641 #define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4 642 #define MEMORY_TRCD_TRANSLATION_TABLE { MEMORY_TRCD_ENTRY_0, \ 643 MEMORY_TRCD_ENTRY_1, \ 644 MEMORY_TRCD_ENTRY_2, \ 645 MEMORY_TRCD_ENTRY_3 } 646 647 648 #define MEMORY_TRCD_PRECISION 0 649 #define MEMORY_TRCD_VALUE_3 2 650 #define MEMORY_TRCD_VALUE_2 3 651 #define MEMORY_TRCD_VALUE_1 4 652 #define MEMORY_TRCD_VALUE_0 5 653 654 #define MEMORY_TRCD_VALUES { MEMORY_TRCD_VALUE_0, \ 655 MEMORY_TRCD_VALUE_1, \ 656 MEMORY_TRCD_VALUE_2, \ 657 MEMORY_TRCD_VALUE_3 } 658 659 660 // 661 // TRP Memory Timing Definitions 662 // 663 664 #define MEMORY_TRP_ENTRY_TYPE UINT8_TYPE 665 #define MEMORY_TRP_ENTRY_3 0x0 666 #define MEMORY_TRP_ENTRY_2 0x1 667 #define MEMORY_TRP_ENTRY_1 0x2 668 #define MEMORY_TRP_ENTRY_0 0x3 669 670 #define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4 671 #define MEMORY_TRP_TRANSLATION_TABLE { MEMORY_TRP_ENTRY_0, \ 672 MEMORY_TRP_ENTRY_1, \ 673 MEMORY_TRP_ENTRY_2, \ 674 MEMORY_TRP_ENTRY_3 } 675 676 677 #define MEMORY_TRP_PRECISION 0 678 #define MEMORY_TRP_VALUE_3 2 679 #define MEMORY_TRP_VALUE_2 3 680 #define MEMORY_TRP_VALUE_1 4 681 #define MEMORY_TRP_VALUE_0 5 682 683 #define MEMORY_TRP_VALUES { MEMORY_TRP_VALUE_0, \ 684 MEMORY_TRP_VALUE_1, \ 685 MEMORY_TRP_VALUE_2, \ 686 MEMORY_TRP_VALUE_3 } 687 688 689 // 690 // TRAS Memory Timing Definitions 691 // 692 #define MEMORY_TRAS_MIN 4 693 #define MEMORY_TRAS_MAX 18 694 #define MEMORY_TRAS_STEP 1 695 #define MEMORY_TRAS_DEFAULT 13 696 #define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX - MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1 697 #define MEMORY_TRAS_TYPE UINT8_TYPE 698 699 // 700 // Uncore Multiplier Definitions 701 // 702 #define UCLK_RATIO_MIN 12 703 #define UCLK_RATIO_MAX 30 704 #define UCLK_RATIO_DEFAULT 20 705 706 #endif // #ifndef _CONFIGURATION_H 707
