1 /******************************************************************************* 2 * Copyright (C) 2018 Cadence Design Systems, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to use this Software with Cadence processor cores only and 7 * not with any other processors and platforms, subject to 8 * the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included 11 * in all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 16 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 17 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 18 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 19 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 21 ******************************************************************************/ 22 #include "xtensa-defs.h" 23 24 .macro SAVE_ reg, loc 25 rsr a1, \reg 26 s32i a1, a3, \loc * 4 27 .endm 28 .macro SAVE reg 29 SAVE_ \reg, \reg 30 .endm 31 32 .macro LOAD_ reg, loc 33 l32i a1, a3, \loc * 4 34 wsr a1, \reg 35 .endm 36 .macro LOAD reg 37 LOAD_ \reg, \reg 38 .endm 39 40 .section ".DebugExceptionVector.text", "ax" 41 .global DebugExceptionVector 42 43 DebugExceptionVector: 44 j 1f 45 .align 4 46 .literal_position 47 1: 48 xsr a2, DEBUG_EXCSAVE 49 jx a2 50 51 .text 52 .global DebugExceptionEntry 53 .align 4 54 55 DebugExceptionEntry: 56 j 1f 57 .align 4 58 .literal_position 59 1: 60 movi a2, aregs 61 s32i a0, a2, 0 62 s32i a1, a2, 4 63 rsr a1, DEBUG_EXCSAVE 64 s32i a1, a2, 8 65 s32i a3, a2, 12 66 67 movi a3, sregs 68 SAVE LBEG 69 SAVE LEND 70 SAVE LCOUNT 71 SAVE SAR 72 SAVE WINDOWBASE 73 SAVE WINDOWSTART 74 75 rsr a1, DEBUG_PC 76 movi a2, initial_breakpoint 77 bne a1, a2, 1f 78 addi a1, a1, 3 79 1: 80 s32i a1, a3, DEBUG_PC * 4 81 82 SAVE EXCSAVE_1 83 SAVE_ DEBUG_PS, PS 84 SAVE EXCCAUSE 85 SAVE DEBUGCAUSE 86 SAVE EXCVADDR 87 88 movi a1, XCHAL_NUM_AREGS / 4 - 1 89 movi a2, aregs 90 1: 91 s32i a4, a2, 16 92 s32i a5, a2, 20 93 s32i a6, a2, 24 94 s32i a7, a2, 28 95 96 addi a6, a2, 16 97 addi a5, a1, -1 98 rotw 1 99 bnez a1, 1b 100 101 movi a1, 1 102 wsr a1, windowstart 103 movi a0, 0 104 wsr a0, windowbase 105 rsync 106 107 movi a0, 0 108 movi a1, stack + STACK_SIZE - 20 109 rsr a2, ps 110 addi a2, a2, -PS_EXCM_MASK 111 wsr a2, ps 112 rsync 113 114 movi a4, handle_exception 115 callx4 a4 116 117 DebugExceptionExit: 118 movi a2, DebugExceptionEntry 119 wsr a2, DEBUG_EXCSAVE 120 121 rsr a2, ps 122 addi a2, a2, PS_EXCM_MASK 123 wsr a2, ps 124 rsync 125 126 movi a3, sregs 127 LOAD LBEG 128 LOAD LEND 129 LOAD LCOUNT 130 /* TODO: handle unlikely return-to-lend case */ 131 LOAD SAR 132 LOAD WINDOWBASE 133 rsync 134 movi a3, sregs 135 LOAD WINDOWSTART 136 LOAD DEBUG_PC 137 LOAD EXCSAVE_1 138 LOAD_ DEBUG_PS, PS 139 LOAD EXCCAUSE 140 LOAD EXCVADDR 141 142 movi a6, aregs 143 movi a5, XCHAL_NUM_AREGS / 4 - 2 144 1: 145 l32i a0, a6, 0 146 l32i a1, a6, 4 147 l32i a2, a6, 8 148 l32i a3, a6, 12 149 150 beqz a5, 2f 151 addi a10, a6, 16 152 addi a9, a5, -1 153 rotw 1 154 j 1b 155 2: 156 l32i a4, a6, 16 157 l32i a5, a6, 20 158 l32i a7, a6, 28 159 l32i a6, a6, 24 160 rotw 2 161 162 rfi XCHAL_DEBUGLEVEL 163 164 165 #ifdef LIBC_LEVEL1_HANDLER 166 .global fault_handler 167 .align 4 168 fault_handler: 169 rsr a2, epc1 170 addi a2, a2, 3 171 wsr a2, epc1 172 rsync 173 movi a2, mem_err 174 s32i a2, a2, 0 175 176 l32i a2, a1, 16 177 l32i a3, a1, 20 178 addi a1, a1, 256 179 rfe 180 #endif 181 182 183 .global init_debug_entry 184 .align 4 185 init_debug_entry: 186 entry a1, 16 187 movi a2, DebugExceptionEntry 188 wsr a2, DEBUG_EXCSAVE 189 isync 190 retw 191 192 .global breakpoint 193 .align 4 194 breakpoint: 195 entry a1, 16 196 initial_breakpoint: 197 _break 0, 0 198 retw 199
