1 /* 2 * Copyright 2013 Red Hat 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #ifndef VIRTGPU_DRM_H 25 #define VIRTGPU_DRM_H 26 27 #include "drm.h" 28 29 #if defined(__cplusplus) 30 extern "C" { 31 #endif 32 33 /* Please note that modifications to all structs defined here are 34 * subject to backwards-compatibility constraints. 35 * 36 * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel 37 * compatibility Keep fields aligned to their size 38 */ 39 40 #define DRM_VIRTGPU_MAP 0x01 41 #define DRM_VIRTGPU_EXECBUFFER 0x02 42 #define DRM_VIRTGPU_GETPARAM 0x03 43 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04 44 #define DRM_VIRTGPU_RESOURCE_INFO 0x05 45 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 46 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 47 #define DRM_VIRTGPU_WAIT 0x08 48 #define DRM_VIRTGPU_GET_CAPS 0x09 49 50 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 51 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 52 #define VIRTGPU_EXECBUF_FLAGS (\ 53 VIRTGPU_EXECBUF_FENCE_FD_IN |\ 54 VIRTGPU_EXECBUF_FENCE_FD_OUT |\ 55 0) 56 57 struct drm_virtgpu_map { 58 __u64 offset; /* use for mmap system call */ 59 __u32 handle; 60 __u32 pad; 61 }; 62 63 struct drm_virtgpu_execbuffer { 64 __u32 flags; 65 __u32 size; 66 __u64 command; /* void* */ 67 __u64 bo_handles; 68 __u32 num_bo_handles; 69 __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ 70 }; 71 72 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ 73 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ 74 75 struct drm_virtgpu_getparam { 76 __u64 param; 77 __u64 value; 78 }; 79 80 /* NO_BO flags? NO resource flag? */ 81 /* resource flag for y_0_top */ 82 struct drm_virtgpu_resource_create { 83 __u32 target; 84 __u32 format; 85 __u32 bind; 86 __u32 width; 87 __u32 height; 88 __u32 depth; 89 __u32 array_size; 90 __u32 last_level; 91 __u32 nr_samples; 92 __u32 flags; 93 __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ 94 __u32 res_handle; /* returned by kernel */ 95 __u32 size; /* validate transfer in the host */ 96 __u32 stride; /* validate transfer in the host */ 97 }; 98 99 struct drm_virtgpu_resource_info { 100 __u32 bo_handle; 101 __u32 res_handle; 102 __u32 size; 103 __u32 stride; 104 }; 105 106 struct drm_virtgpu_3d_box { 107 __u32 x; 108 __u32 y; 109 __u32 z; 110 __u32 w; 111 __u32 h; 112 __u32 d; 113 }; 114 115 struct drm_virtgpu_3d_transfer_to_host { 116 __u32 bo_handle; 117 struct drm_virtgpu_3d_box box; 118 __u32 level; 119 __u32 offset; 120 }; 121 122 struct drm_virtgpu_3d_transfer_from_host { 123 __u32 bo_handle; 124 struct drm_virtgpu_3d_box box; 125 __u32 level; 126 __u32 offset; 127 }; 128 129 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ 130 struct drm_virtgpu_3d_wait { 131 __u32 handle; /* 0 is an invalid handle */ 132 __u32 flags; 133 }; 134 135 struct drm_virtgpu_get_caps { 136 __u32 cap_set_id; 137 __u32 cap_set_ver; 138 __u64 addr; 139 __u32 size; 140 __u32 pad; 141 }; 142 143 #define DRM_IOCTL_VIRTGPU_MAP \ 144 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) 145 146 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \ 147 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ 148 struct drm_virtgpu_execbuffer) 149 150 #define DRM_IOCTL_VIRTGPU_GETPARAM \ 151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ 152 struct drm_virtgpu_getparam) 153 154 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ 156 struct drm_virtgpu_resource_create) 157 158 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ 159 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ 160 struct drm_virtgpu_resource_info) 161 162 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ 163 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ 164 struct drm_virtgpu_3d_transfer_from_host) 165 166 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ 167 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ 168 struct drm_virtgpu_3d_transfer_to_host) 169 170 #define DRM_IOCTL_VIRTGPU_WAIT \ 171 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ 172 struct drm_virtgpu_3d_wait) 173 174 #define DRM_IOCTL_VIRTGPU_GET_CAPS \ 175 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ 176 struct drm_virtgpu_get_caps) 177 178 #if defined(__cplusplus) 179 } 180 #endif 181 182 #endif 183
