1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 #include <rdma/ib_user_ioctl_verbs.h> 40 41 enum { 42 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 48 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6, 49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7, 50 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8, 51 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9, 52 }; 53 54 enum { 55 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 56 }; 57 58 enum { 59 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 60 }; 61 62 /* Increment this value if any changes that break userspace ABI 63 * compatibility are made. 64 */ 65 #define MLX5_IB_UVERBS_ABI_VERSION 1 66 67 /* Make sure that all structs defined in this file remain laid out so 68 * that they pack the same way on 32-bit and 64-bit architectures (to 69 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 70 * In particular do not use pointer types -- pass pointers in __u64 71 * instead. 72 */ 73 74 struct mlx5_ib_alloc_ucontext_req { 75 __u32 total_num_bfregs; 76 __u32 num_low_latency_bfregs; 77 }; 78 79 enum mlx5_lib_caps { 80 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 81 }; 82 83 enum mlx5_ib_alloc_uctx_v2_flags { 84 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 85 }; 86 struct mlx5_ib_alloc_ucontext_req_v2 { 87 __u32 total_num_bfregs; 88 __u32 num_low_latency_bfregs; 89 __u32 flags; 90 __u32 comp_mask; 91 __u8 max_cqe_version; 92 __u8 reserved0; 93 __u16 reserved1; 94 __u32 reserved2; 95 __aligned_u64 lib_caps; 96 }; 97 98 enum mlx5_ib_alloc_ucontext_resp_mask { 99 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 100 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1, 101 }; 102 103 enum mlx5_user_cmds_supp_uhw { 104 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 105 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 106 }; 107 108 /* The eth_min_inline response value is set to off-by-one vs the FW 109 * returned value to allow user-space to deal with older kernels. 110 */ 111 enum mlx5_user_inline_mode { 112 MLX5_USER_INLINE_MODE_NA, 113 MLX5_USER_INLINE_MODE_NONE, 114 MLX5_USER_INLINE_MODE_L2, 115 MLX5_USER_INLINE_MODE_IP, 116 MLX5_USER_INLINE_MODE_TCP_UDP, 117 }; 118 119 enum { 120 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, 121 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, 122 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, 123 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, 124 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, 125 }; 126 127 struct mlx5_ib_alloc_ucontext_resp { 128 __u32 qp_tab_size; 129 __u32 bf_reg_size; 130 __u32 tot_bfregs; 131 __u32 cache_line_size; 132 __u16 max_sq_desc_sz; 133 __u16 max_rq_desc_sz; 134 __u32 max_send_wqebb; 135 __u32 max_recv_wr; 136 __u32 max_srq_recv_wr; 137 __u16 num_ports; 138 __u16 flow_action_flags; 139 __u32 comp_mask; 140 __u32 response_length; 141 __u8 cqe_version; 142 __u8 cmds_supp_uhw; 143 __u8 eth_min_inline; 144 __u8 clock_info_versions; 145 __aligned_u64 hca_core_clock_offset; 146 __u32 log_uar_size; 147 __u32 num_uars_per_page; 148 __u32 num_dyn_bfregs; 149 __u32 dump_fill_mkey; 150 }; 151 152 struct mlx5_ib_alloc_pd_resp { 153 __u32 pdn; 154 }; 155 156 struct mlx5_ib_tso_caps { 157 __u32 max_tso; /* Maximum tso payload size in bytes */ 158 159 /* Corresponding bit will be set if qp type from 160 * 'enum ib_qp_type' is supported, e.g. 161 * supported_qpts |= 1 << IB_QPT_UD 162 */ 163 __u32 supported_qpts; 164 }; 165 166 struct mlx5_ib_rss_caps { 167 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 168 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 169 __u8 reserved[7]; 170 }; 171 172 enum mlx5_ib_cqe_comp_res_format { 173 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 174 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 175 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, 176 }; 177 178 struct mlx5_ib_cqe_comp_caps { 179 __u32 max_num; 180 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 181 }; 182 183 enum mlx5_ib_packet_pacing_cap_flags { 184 MLX5_IB_PP_SUPPORT_BURST = 1 << 0, 185 }; 186 187 struct mlx5_packet_pacing_caps { 188 __u32 qp_rate_limit_min; 189 __u32 qp_rate_limit_max; /* In kpbs */ 190 191 /* Corresponding bit will be set if qp type from 192 * 'enum ib_qp_type' is supported, e.g. 193 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 194 */ 195 __u32 supported_qpts; 196 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */ 197 __u8 reserved[3]; 198 }; 199 200 enum mlx5_ib_mpw_caps { 201 MPW_RESERVED = 1 << 0, 202 MLX5_IB_ALLOW_MPW = 1 << 1, 203 MLX5_IB_SUPPORT_EMPW = 1 << 2, 204 }; 205 206 enum mlx5_ib_sw_parsing_offloads { 207 MLX5_IB_SW_PARSING = 1 << 0, 208 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 209 MLX5_IB_SW_PARSING_LSO = 1 << 2, 210 }; 211 212 struct mlx5_ib_sw_parsing_caps { 213 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 214 215 /* Corresponding bit will be set if qp type from 216 * 'enum ib_qp_type' is supported, e.g. 217 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 218 */ 219 __u32 supported_qpts; 220 }; 221 222 struct mlx5_ib_striding_rq_caps { 223 __u32 min_single_stride_log_num_of_bytes; 224 __u32 max_single_stride_log_num_of_bytes; 225 __u32 min_single_wqe_log_num_of_strides; 226 __u32 max_single_wqe_log_num_of_strides; 227 228 /* Corresponding bit will be set if qp type from 229 * 'enum ib_qp_type' is supported, e.g. 230 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 231 */ 232 __u32 supported_qpts; 233 __u32 reserved; 234 }; 235 236 enum mlx5_ib_query_dev_resp_flags { 237 /* Support 128B CQE compression */ 238 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 239 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 240 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2, 241 }; 242 243 enum mlx5_ib_tunnel_offloads { 244 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 245 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 246 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, 247 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, 248 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, 249 }; 250 251 struct mlx5_ib_query_device_resp { 252 __u32 comp_mask; 253 __u32 response_length; 254 struct mlx5_ib_tso_caps tso_caps; 255 struct mlx5_ib_rss_caps rss_caps; 256 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 257 struct mlx5_packet_pacing_caps packet_pacing_caps; 258 __u32 mlx5_ib_support_multi_pkt_send_wqes; 259 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 260 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 261 struct mlx5_ib_striding_rq_caps striding_rq_caps; 262 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 263 __u32 reserved; 264 }; 265 266 enum mlx5_ib_create_cq_flags { 267 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 268 }; 269 270 struct mlx5_ib_create_cq { 271 __aligned_u64 buf_addr; 272 __aligned_u64 db_addr; 273 __u32 cqe_size; 274 __u8 cqe_comp_en; 275 __u8 cqe_comp_res_format; 276 __u16 flags; 277 }; 278 279 struct mlx5_ib_create_cq_resp { 280 __u32 cqn; 281 __u32 reserved; 282 }; 283 284 struct mlx5_ib_resize_cq { 285 __aligned_u64 buf_addr; 286 __u16 cqe_size; 287 __u16 reserved0; 288 __u32 reserved1; 289 }; 290 291 struct mlx5_ib_create_srq { 292 __aligned_u64 buf_addr; 293 __aligned_u64 db_addr; 294 __u32 flags; 295 __u32 reserved0; /* explicit padding (optional on i386) */ 296 __u32 uidx; 297 __u32 reserved1; 298 }; 299 300 struct mlx5_ib_create_srq_resp { 301 __u32 srqn; 302 __u32 reserved; 303 }; 304 305 struct mlx5_ib_create_qp { 306 __aligned_u64 buf_addr; 307 __aligned_u64 db_addr; 308 __u32 sq_wqe_count; 309 __u32 rq_wqe_count; 310 __u32 rq_wqe_shift; 311 __u32 flags; 312 __u32 uidx; 313 __u32 bfreg_index; 314 union { 315 __aligned_u64 sq_buf_addr; 316 __aligned_u64 access_key; 317 }; 318 }; 319 320 /* RX Hash function flags */ 321 enum mlx5_rx_hash_function_flags { 322 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 323 }; 324 325 /* 326 * RX Hash flags, these flags allows to set which incoming packet's field should 327 * participates in RX Hash. Each flag represent certain packet's field, 328 * when the flag is set the field that is represented by the flag will 329 * participate in RX Hash calculation. 330 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 331 * and *TCP and *UDP flags can't be enabled together on the same QP. 332 */ 333 enum mlx5_rx_hash_fields { 334 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 335 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 336 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 337 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 338 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 339 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 340 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 341 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 342 MLX5_RX_HASH_IPSEC_SPI = 1 << 8, 343 /* Save bits for future fields */ 344 MLX5_RX_HASH_INNER = (1UL << 31), 345 }; 346 347 struct mlx5_ib_create_qp_rss { 348 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 349 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 350 __u8 rx_key_len; /* valid only for Toeplitz */ 351 __u8 reserved[6]; 352 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 353 __u32 comp_mask; 354 __u32 flags; 355 }; 356 357 enum mlx5_ib_create_qp_resp_mask { 358 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0, 359 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1, 360 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2, 361 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3, 362 }; 363 364 struct mlx5_ib_create_qp_resp { 365 __u32 bfreg_index; 366 __u32 reserved; 367 __u32 comp_mask; 368 __u32 tirn; 369 __u32 tisn; 370 __u32 rqn; 371 __u32 sqn; 372 __u32 reserved1; 373 }; 374 375 struct mlx5_ib_alloc_mw { 376 __u32 comp_mask; 377 __u8 num_klms; 378 __u8 reserved1; 379 __u16 reserved2; 380 }; 381 382 enum mlx5_ib_create_wq_mask { 383 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 384 }; 385 386 struct mlx5_ib_create_wq { 387 __aligned_u64 buf_addr; 388 __aligned_u64 db_addr; 389 __u32 rq_wqe_count; 390 __u32 rq_wqe_shift; 391 __u32 user_index; 392 __u32 flags; 393 __u32 comp_mask; 394 __u32 single_stride_log_num_of_bytes; 395 __u32 single_wqe_log_num_of_strides; 396 __u32 two_byte_shift_en; 397 }; 398 399 struct mlx5_ib_create_ah_resp { 400 __u32 response_length; 401 __u8 dmac[ETH_ALEN]; 402 __u8 reserved[6]; 403 }; 404 405 struct mlx5_ib_burst_info { 406 __u32 max_burst_sz; 407 __u16 typical_pkt_sz; 408 __u16 reserved; 409 }; 410 411 struct mlx5_ib_modify_qp { 412 __u32 comp_mask; 413 struct mlx5_ib_burst_info burst_info; 414 __u32 reserved; 415 }; 416 417 struct mlx5_ib_modify_qp_resp { 418 __u32 response_length; 419 __u32 dctn; 420 }; 421 422 struct mlx5_ib_create_wq_resp { 423 __u32 response_length; 424 __u32 reserved; 425 }; 426 427 struct mlx5_ib_create_rwq_ind_tbl_resp { 428 __u32 response_length; 429 __u32 reserved; 430 }; 431 432 struct mlx5_ib_modify_wq { 433 __u32 comp_mask; 434 __u32 reserved; 435 }; 436 437 struct mlx5_ib_clock_info { 438 __u32 sign; 439 __u32 resv; 440 __aligned_u64 nsec; 441 __aligned_u64 cycles; 442 __aligned_u64 frac; 443 __u32 mult; 444 __u32 shift; 445 __aligned_u64 mask; 446 __aligned_u64 overflow_period; 447 }; 448 449 enum mlx5_ib_mmap_cmd { 450 MLX5_IB_MMAP_REGULAR_PAGE = 0, 451 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 452 MLX5_IB_MMAP_WC_PAGE = 2, 453 MLX5_IB_MMAP_NC_PAGE = 3, 454 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 455 MLX5_IB_MMAP_CORE_CLOCK = 5, 456 MLX5_IB_MMAP_ALLOC_WC = 6, 457 MLX5_IB_MMAP_CLOCK_INFO = 7, 458 MLX5_IB_MMAP_DEVICE_MEM = 8, 459 }; 460 461 enum { 462 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 463 }; 464 465 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 466 enum { 467 MLX5_IB_CLOCK_INFO_V1 = 0, 468 }; 469 470 struct mlx5_ib_flow_counters_desc { 471 __u32 description; 472 __u32 index; 473 }; 474 475 struct mlx5_ib_flow_counters_data { 476 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 477 __u32 ncounters; 478 __u32 reserved; 479 }; 480 481 struct mlx5_ib_create_flow { 482 __u32 ncounters_data; 483 __u32 reserved; 484 /* 485 * Following are counters data based on ncounters_data, each 486 * entry in the data[] should match a corresponding counter object 487 * that was pointed by a counters spec upon the flow creation 488 */ 489 struct mlx5_ib_flow_counters_data data[]; 490 }; 491 492 #endif /* MLX5_ABI_USER_H */ 493
