1 /****************************************************************************** 2 * 3 * Copyright (C) 2018 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 21 /*! 22 ****************************************************************************** 23 * \file ihevce_tile_interface.c 24 * 25 * \brief 26 * This file contains functions related to tile interface 27 * 28 * \date 29 * 24/10/2012 30 * 31 * \author 32 * Ittiam 33 * 34 * 35 * List of Functions 36 * 37 * 38 ****************************************************************************** 39 */ 40 41 /*****************************************************************************/ 42 /* File Includes */ 43 /*****************************************************************************/ 44 /* System include files */ 45 #include <string.h> 46 #include <stdio.h> 47 #include <stdlib.h> 48 #include <assert.h> 49 50 /* User include files */ 51 #include "ihevc_typedefs.h" 52 #include "itt_video_api.h" 53 #include "ihevce_api.h" 54 55 #include "rc_cntrl_param.h" 56 #include "rc_frame_info_collector.h" 57 #include "rc_look_ahead_params.h" 58 59 #include "ihevc_defs.h" 60 #include "ihevc_structs.h" 61 #include "ihevc_platform_macros.h" 62 #include "ihevc_deblk.h" 63 #include "ihevc_itrans_recon.h" 64 #include "ihevc_chroma_itrans_recon.h" 65 #include "ihevc_chroma_intra_pred.h" 66 #include "ihevc_intra_pred.h" 67 #include "ihevc_inter_pred.h" 68 #include "ihevc_mem_fns.h" 69 #include "ihevc_padding.h" 70 #include "ihevc_weighted_pred.h" 71 #include "ihevc_sao.h" 72 #include "ihevc_resi_trans.h" 73 #include "ihevc_quant_iquant_ssd.h" 74 #include "ihevc_cabac_tables.h" 75 76 #include "ihevce_defs.h" 77 #include "ihevce_lap_enc_structs.h" 78 #include "ihevce_multi_thrd_structs.h" 79 #include "ihevce_me_common_defs.h" 80 #include "ihevce_had_satd.h" 81 #include "ihevce_error_codes.h" 82 #include "ihevce_bitstream.h" 83 #include "ihevce_cabac.h" 84 #include "ihevce_rdoq_macros.h" 85 #include "ihevce_function_selector.h" 86 #include "ihevce_enc_structs.h" 87 #include "ihevce_entropy_structs.h" 88 #include "ihevce_cmn_utils_instr_set_router.h" 89 #include "ihevce_enc_loop_structs.h" 90 #include "ihevce_tile_interface.h" 91 92 /*****************************************************************************/ 93 /* Function Definitions */ 94 /*****************************************************************************/ 95 96 /*! 97 ****************************************************************************** 98 * \if Function name : ihevce_update_tile_params \endif 99 * 100 * \brief 101 * Updates the ps_tile_params structres based on the tile-position in frame. 102 * 103 ***************************************************************************** 104 */ 105 void ihevce_update_tile_params( 106 ihevce_static_cfg_params_t *ps_static_cfg_prms, 107 ihevce_tile_params_t *ps_tile_params, 108 WORD32 i4_resolution_id) 109 { 110 /* Total number of tiles in a frame */ 111 ihevce_app_tile_params_t *ps_app_tile_prms; 112 WORD32 i4_num_tiles; 113 WORD32 i4_cu_aligned_tgt_frame_ht, 114 i4_cu_aligned_tgt_frame_wd; //Frame width and height specific to target-resolution 115 WORD32 i4_ctb_aligned_tgt_frame_ht, 116 i4_ctb_aligned_tgt_frame_wd; //Frame width and height specific to target-resolution 117 WORD32 i4_x_y = 0; 118 WORD32 i4_pos; 119 WORD32 i4_i; 120 121 WORD32 i4_curr_tile_id; 122 WORD32 i4_max_log2_cu_size, i4_ctb_size; 123 WORD32 i4_pic_wd_in_ctb; 124 WORD32 i4_pic_ht_in_ctb; 125 WORD32 min_cu_size; 126 WORD32 i4_num_tile_cols = 1; 127 WORD32 i4_num_tile_rows = 1; 128 129 ps_app_tile_prms = &ps_static_cfg_prms->s_app_tile_params; 130 131 i4_max_log2_cu_size = ps_static_cfg_prms->s_config_prms.i4_max_log2_cu_size; 132 i4_ctb_size = 1 << i4_max_log2_cu_size; 133 134 min_cu_size = 1 << ps_static_cfg_prms->s_config_prms.i4_min_log2_cu_size; 135 136 /* Allign the frame width to min CU size */ 137 i4_cu_aligned_tgt_frame_wd = 138 ps_static_cfg_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_width + 139 SET_CTB_ALIGN( 140 ps_static_cfg_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_width, 141 min_cu_size); 142 143 /* Allign the frame hieght to min CU size */ 144 i4_cu_aligned_tgt_frame_ht = 145 ps_static_cfg_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_height + 146 SET_CTB_ALIGN( 147 ps_static_cfg_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_height, 148 min_cu_size); 149 150 if(1 == ps_app_tile_prms->i4_tiles_enabled_flag) 151 { 152 i4_num_tile_cols = ps_app_tile_prms->i4_num_tile_cols; 153 i4_num_tile_rows = ps_app_tile_prms->i4_num_tile_rows; 154 } 155 156 i4_num_tiles = i4_num_tile_cols * i4_num_tile_rows; 157 158 i4_ctb_aligned_tgt_frame_wd = i4_cu_aligned_tgt_frame_wd; 159 i4_ctb_aligned_tgt_frame_wd += SET_CTB_ALIGN(i4_ctb_aligned_tgt_frame_wd, MAX_CTB_SIZE); 160 i4_pic_wd_in_ctb = i4_ctb_aligned_tgt_frame_wd >> i4_max_log2_cu_size; 161 162 i4_ctb_aligned_tgt_frame_ht = i4_cu_aligned_tgt_frame_ht; 163 i4_ctb_aligned_tgt_frame_ht += SET_CTB_ALIGN(i4_ctb_aligned_tgt_frame_ht, MAX_CTB_SIZE); 164 i4_pic_ht_in_ctb = i4_ctb_aligned_tgt_frame_ht >> i4_max_log2_cu_size; 165 166 /* Update tile enable flag in each instance's tile struct */ 167 ps_tile_params->i4_tiles_enabled_flag = ps_app_tile_prms->i4_tiles_enabled_flag; 168 169 ps_tile_params->i4_num_tile_cols = i4_num_tile_cols; 170 ps_tile_params->i4_num_tile_rows = i4_num_tile_rows; 171 172 i4_curr_tile_id = ps_tile_params->i4_curr_tile_id; 173 174 /* num tiles in frame */ 175 ps_tile_params->i4_num_tiles = i4_num_tiles; 176 177 ps_tile_params->i4_uniform_spacing_flag = ps_app_tile_prms->i4_uniform_spacing_flag; 178 179 if(0 == ps_tile_params->i4_tiles_enabled_flag) 180 { 181 /* curr tile width and height */ 182 ps_tile_params->i4_curr_tile_width = i4_cu_aligned_tgt_frame_wd; 183 ps_tile_params->i4_curr_tile_height = i4_cu_aligned_tgt_frame_ht; 184 185 ps_tile_params->i4_first_ctb_x = 0; 186 ps_tile_params->i4_first_ctb_y = 0; 187 188 ps_tile_params->i4_first_sample_x = 0; 189 ps_tile_params->i4_first_sample_y = 0; 190 } 191 else 192 { 193 if(0 == ps_app_tile_prms->i4_uniform_spacing_flag) 194 { 195 /* curr tile width */ 196 ps_tile_params->i4_curr_tile_width = 197 ps_app_tile_prms->ai4_column_width[i4_curr_tile_id % i4_num_tile_cols]; 198 199 /* curr tile height */ 200 ps_tile_params->i4_curr_tile_height = 201 ps_app_tile_prms->ai4_row_height[i4_curr_tile_id / i4_num_tile_cols]; 202 203 /* ctb_x and ctb_y of first ctb in tile */ 204 i4_pos = i4_curr_tile_id % i4_num_tile_cols; 205 206 for(i4_i = 0; i4_i < i4_pos; i4_i++) 207 { 208 i4_x_y += ps_app_tile_prms->ai4_column_width[i4_i]; 209 } 210 211 ps_tile_params->i4_first_sample_x = i4_x_y; 212 ps_tile_params->i4_first_ctb_x = i4_x_y >> i4_max_log2_cu_size; 213 214 i4_pos = i4_curr_tile_id / i4_num_tile_cols; 215 216 i4_x_y = 0; 217 218 for(i4_i = 0; i4_i < i4_pos; i4_i++) 219 { 220 i4_x_y += ps_app_tile_prms->ai4_row_height[i4_i]; 221 } 222 223 ps_tile_params->i4_first_sample_y = i4_x_y; 224 ps_tile_params->i4_first_ctb_y = i4_x_y >> i4_max_log2_cu_size; 225 } 226 else 227 { 228 /* below formula for tile width/height and start_x/start_y are derived from HM Decoder */ 229 WORD32 i4_start = 0; 230 WORD32 i4_value = 0; 231 /* curr tile width */ 232 for(i4_i = 0; i4_i < i4_num_tile_cols; i4_i++) 233 { 234 i4_value = ((i4_i + 1) * i4_pic_wd_in_ctb) / i4_num_tile_cols - 235 (i4_i * i4_pic_wd_in_ctb) / i4_num_tile_cols; 236 237 if(i4_i == (i4_curr_tile_id % i4_num_tile_cols)) 238 { 239 ps_tile_params->i4_first_ctb_x = i4_start; 240 ps_tile_params->i4_first_sample_x = (i4_start << i4_max_log2_cu_size); 241 ps_tile_params->i4_curr_tile_width = (i4_value << i4_max_log2_cu_size); 242 if(i4_i == (i4_num_tile_cols - 1)) 243 { 244 if(i4_cu_aligned_tgt_frame_wd % i4_ctb_size) 245 { 246 ps_tile_params->i4_curr_tile_width = 247 (ps_tile_params->i4_curr_tile_width - i4_ctb_size) + 248 (i4_cu_aligned_tgt_frame_wd % i4_ctb_size); 249 } 250 } 251 break; 252 } 253 i4_start += i4_value; 254 } 255 256 /* curr tile height */ 257 i4_start = 0; 258 for(i4_i = 0; i4_i < i4_num_tile_rows; i4_i++) 259 { 260 i4_value = ((i4_i + 1) * i4_pic_ht_in_ctb) / i4_num_tile_rows - 261 (i4_i * i4_pic_ht_in_ctb) / i4_num_tile_rows; 262 263 if(i4_i == (i4_curr_tile_id / i4_num_tile_cols)) 264 { 265 ps_tile_params->i4_first_ctb_y = i4_start; 266 ps_tile_params->i4_first_sample_y = (i4_start << i4_max_log2_cu_size); 267 ps_tile_params->i4_curr_tile_height = (i4_value << i4_max_log2_cu_size); 268 if(i4_i == (i4_num_tile_rows - 1)) 269 { 270 if(i4_cu_aligned_tgt_frame_ht % i4_ctb_size) 271 { 272 ps_tile_params->i4_curr_tile_height = 273 (ps_tile_params->i4_curr_tile_height - i4_ctb_size) + 274 (i4_cu_aligned_tgt_frame_ht % i4_ctb_size); 275 } 276 } 277 break; 278 } 279 i4_start += i4_value; 280 } 281 } 282 } 283 284 /* Initiallize i4_curr_tile_wd_in_ctb_unit and i4_curr_tile_ht_in_ctb_unit */ 285 ps_tile_params->i4_curr_tile_wd_in_ctb_unit = 286 ps_tile_params->i4_curr_tile_width + 287 SET_CTB_ALIGN(ps_tile_params->i4_curr_tile_width, i4_ctb_size); 288 289 ps_tile_params->i4_curr_tile_ht_in_ctb_unit = 290 ps_tile_params->i4_curr_tile_height + 291 SET_CTB_ALIGN(ps_tile_params->i4_curr_tile_height, i4_ctb_size); 292 293 ps_tile_params->i4_curr_tile_wd_in_ctb_unit /= i4_ctb_size; 294 ps_tile_params->i4_curr_tile_ht_in_ctb_unit /= i4_ctb_size; 295 } 296 297 /*! 298 ****************************************************************************** 299 * \if Function name : ihevce_tiles_get_num_mem_recs \endif 300 * 301 * \brief 302 * Returns the total no. of memory records needed for tile encoding 303 * 304 * \param 305 * None 306 * 307 * \return 308 * total no. of memory required 309 * 310 * \author 311 * Ittiam 312 * 313 ***************************************************************************** 314 */ 315 WORD32 ihevce_tiles_get_num_mem_recs(void) 316 { 317 WORD32 i4_total_memtabs_req = 0; 318 319 /*------------------------------------------------------------------*/ 320 /* Get number of memtabs */ 321 /*------------------------------------------------------------------*/ 322 /* Memory for keeping all tile's parameters */ 323 i4_total_memtabs_req++; 324 325 /* Memory for keeping frame level tile_id map */ 326 i4_total_memtabs_req++; 327 328 return (i4_total_memtabs_req); 329 } 330 331 /*! 332 ****************************************************************************** 333 * \if Function name : ihevce_tiles_get_mem_recs \endif 334 * 335 * \brief 336 * Fills each memory record attributes of tiles 337 * 338 * \param[in,out] ps_mem_tab : pointer to memory descriptors table 339 * \param[in] ps_tile_master_prms : master tile params 340 * \param[in] i4_mem_space : memspace in whihc memory request should be done 341 * 342 * \return 343 * total no. of mem records filled 344 * 345 * \author 346 * Ittiam 347 * 348 ***************************************************************************** 349 */ 350 WORD32 ihevce_tiles_get_mem_recs( 351 iv_mem_rec_t *ps_memtab, 352 ihevce_static_cfg_params_t *ps_static_cfg_params, 353 frm_ctb_ctxt_t *ps_frm_ctb_prms, 354 WORD32 i4_resolution_id, 355 WORD32 i4_mem_space) 356 { 357 //WORD32 i4_frame_width, i4_frame_height; 358 WORD32 i4_num_tiles; 359 WORD32 i4_total_memtabs_filled = 0; 360 WORD32 i4_num_tile_cols = 1; 361 WORD32 i4_num_tile_rows = 1; 362 WORD32 ctb_aligned_frame_width, ctb_aligned_frame_height; 363 WORD32 u4_ctb_in_a_row, u4_ctb_rows_in_a_frame; 364 365 ihevce_app_tile_params_t *ps_app_tile_params = &ps_static_cfg_params->s_app_tile_params; 366 /* 367 i4_frame_width = ps_tile_master_prms->i4_frame_width; 368 i4_frame_height = ps_tile_master_prms->i4_frame_height;*/ 369 370 if(1 == ps_app_tile_params->i4_tiles_enabled_flag) 371 { 372 i4_num_tile_cols = ps_app_tile_params->i4_num_tile_cols; 373 i4_num_tile_rows = ps_app_tile_params->i4_num_tile_rows; 374 } 375 376 i4_num_tiles = i4_num_tile_cols * i4_num_tile_rows; 377 378 /* -------- Memory for storing all tile params ---------*/ 379 ps_memtab[0].i4_size = sizeof(iv_mem_rec_t); 380 ps_memtab[0].i4_mem_size = i4_num_tiles * sizeof(ihevce_tile_params_t); 381 ps_memtab[0].e_mem_type = (IV_MEM_TYPE_T)i4_mem_space; 382 ps_memtab[0].i4_mem_alignment = 8; 383 i4_total_memtabs_filled++; 384 385 /* -------- Memory for CTB level tile-id map ---------*/ 386 ctb_aligned_frame_width = 387 ps_static_cfg_params->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_width; 388 ctb_aligned_frame_height = 389 ps_static_cfg_params->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_height; 390 391 /*making the width and height a multiple of CTB size*/ 392 ctb_aligned_frame_width += SET_CTB_ALIGN( 393 ps_static_cfg_params->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_width, 394 MAX_CTB_SIZE); 395 ctb_aligned_frame_height += SET_CTB_ALIGN( 396 ps_static_cfg_params->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_height, 397 MAX_CTB_SIZE); 398 399 u4_ctb_in_a_row = (ctb_aligned_frame_width / MAX_CTB_SIZE); 400 u4_ctb_rows_in_a_frame = (ctb_aligned_frame_height / MAX_CTB_SIZE); 401 402 ps_frm_ctb_prms->i4_tile_id_ctb_map_stride = (ctb_aligned_frame_width / MAX_CTB_SIZE); 403 404 /* Memory for a frame level memory to store tile-id corresponding to each CTB of frame*/ 405 /* (u4_ctb_in_a_row + 1): Keeping an extra column on the left. Tile Id's will be set to -1 in it */ 406 /* (u4_ctb_rows_in_a_frame + 1): Keeping an extra column on the top. Tile Id's will be set to -1 in it */ 407 /* -1 -1 -1 -1 -1 -1 -1 ....... -1 -1 408 -1 0 0 1 1 2 2 ....... M -1 409 -1 0 0 1 1 2 2 ....... M -1 410 .. .. .. .. .. .. .. ....... M -1 411 .. .. .. .. .. .. .. ....... M -1 412 -1 N N N+1 N+1 N+2 N+2 ....... N+M -1 413 */ 414 ps_memtab[1].i4_size = sizeof(iv_mem_rec_t); 415 ps_memtab[1].i4_mem_size = 416 (1 + u4_ctb_in_a_row + 1) * (1 + u4_ctb_rows_in_a_frame) * sizeof(WORD32); 417 ps_memtab[1].e_mem_type = (IV_MEM_TYPE_T)i4_mem_space; 418 ps_memtab[1].i4_mem_alignment = 8; 419 i4_total_memtabs_filled++; 420 421 return (i4_total_memtabs_filled); 422 } 423 424 /*! 425 ****************************************************************************** 426 * \if Function name : ihevce_tiles_mem_init \endif 427 * 428 * \brief 429 * Initialization of shared buffer memories 430 * 431 * \param[in] ps_mem_tab : pointer to memory descriptors table 432 * \param[in] ps_tile_master_prms : master tile params 433 * 434 * \return 435 * None 436 * 437 * \author 438 * Ittiam 439 * 440 ***************************************************************************** 441 */ 442 void *ihevce_tiles_mem_init( 443 iv_mem_rec_t *ps_memtab, 444 ihevce_static_cfg_params_t *ps_static_cfg_prms, 445 enc_ctxt_t *ps_enc_ctxt, 446 WORD32 i4_resolution_id) 447 { 448 WORD32 i4_num_tiles, tile_ctr; 449 WORD32 ctb_row_ctr, ctb_col_ctr, i; 450 WORD32 tile_pos_x, tile_pos_y; 451 WORD32 tile_wd_in_ctb, tile_ht_in_ctb; 452 WORD32 *pi4_tile_id_map_temp, *pi4_tile_id_map_base; 453 WORD32 frame_width_in_ctb; 454 WORD32 i4_num_tile_cols = 1; 455 WORD32 i4_num_tile_rows = 1; 456 457 ihevce_tile_params_t *ps_tile_params_base; 458 frm_ctb_ctxt_t *ps_frm_ctb_prms = &ps_enc_ctxt->s_frm_ctb_prms; 459 460 if(1 == ps_static_cfg_prms->s_app_tile_params.i4_tiles_enabled_flag) 461 { 462 i4_num_tile_cols = ps_static_cfg_prms->s_app_tile_params.i4_num_tile_cols; 463 i4_num_tile_rows = ps_static_cfg_prms->s_app_tile_params.i4_num_tile_rows; 464 } 465 466 frame_width_in_ctb = 467 ps_static_cfg_prms->s_tgt_lyr_prms.as_tgt_params[i4_resolution_id].i4_width; 468 frame_width_in_ctb += SET_CTB_ALIGN(frame_width_in_ctb, MAX_CTB_SIZE); 469 frame_width_in_ctb /= MAX_CTB_SIZE; 470 471 /* -------- Memory for storing all tile params ---------*/ 472 ps_tile_params_base = (ihevce_tile_params_t *)ps_memtab->pv_base; 473 ps_memtab++; 474 475 i4_num_tiles = i4_num_tile_cols * i4_num_tile_rows; 476 477 for(tile_ctr = 0; tile_ctr < i4_num_tiles; tile_ctr++) 478 { 479 WORD32 i4_i; 480 ihevce_tile_params_t *ps_tile_params = (ps_tile_params_base + tile_ctr); 481 482 /* Setting default values */ 483 memset(ps_tile_params, 0, sizeof(ihevce_tile_params_t)); 484 485 ps_tile_params->i4_curr_tile_id = tile_ctr; /* tile id */ 486 487 /* update create time tile params in each encoder context */ 488 ihevce_update_tile_params(ps_static_cfg_prms, ps_tile_params, i4_resolution_id); 489 490 if(0 == ps_static_cfg_prms->s_app_tile_params.i4_uniform_spacing_flag) 491 { 492 /* Storing column width array and row height array inro enc ctxt */ 493 for(i4_i = 0; i4_i < i4_num_tile_cols; i4_i++) 494 { 495 ps_enc_ctxt->ai4_column_width_array[i4_i] = 496 ps_static_cfg_prms->s_app_tile_params.ai4_column_width[i4_i]; 497 } 498 for(i4_i = 0; i4_i < i4_num_tile_rows; i4_i++) 499 { 500 ps_enc_ctxt->ai4_row_height_array[i4_i] = 501 ps_static_cfg_prms->s_app_tile_params.ai4_row_height[i4_i]; 502 } 503 } 504 } 505 506 /* -------- Memory for CTB level tile-id map ---------*/ 507 pi4_tile_id_map_base = (WORD32 *)ps_memtab->pv_base; 508 509 // An extra col and row at top, left and right aroun frame level memory. Is set to -1. 510 ps_frm_ctb_prms->i4_tile_id_ctb_map_stride = frame_width_in_ctb + 2; 511 ps_frm_ctb_prms->pi4_tile_id_map = 512 pi4_tile_id_map_base + ps_frm_ctb_prms->i4_tile_id_ctb_map_stride + 1; 513 ps_memtab++; 514 515 /* Filling -1 in top row */ 516 for(i = 0; i < ps_frm_ctb_prms->i4_tile_id_ctb_map_stride; i++) 517 { 518 pi4_tile_id_map_base[i] = -1; 519 } 520 521 /* Now creating tile-id map */ 522 for(tile_ctr = 0; tile_ctr < ps_tile_params_base->i4_num_tiles; tile_ctr++) 523 { 524 ihevce_tile_params_t *ps_tile_params = ps_tile_params_base + tile_ctr; 525 526 tile_pos_x = ps_tile_params->i4_first_ctb_x; 527 tile_pos_y = ps_tile_params->i4_first_ctb_y; 528 tile_wd_in_ctb = ps_tile_params->i4_curr_tile_wd_in_ctb_unit; 529 tile_ht_in_ctb = ps_tile_params->i4_curr_tile_ht_in_ctb_unit; 530 531 pi4_tile_id_map_temp = ps_frm_ctb_prms->pi4_tile_id_map + 532 tile_pos_y * ps_frm_ctb_prms->i4_tile_id_ctb_map_stride + tile_pos_x; 533 534 for(ctb_row_ctr = 0; (ctb_row_ctr < tile_ht_in_ctb); ctb_row_ctr++) 535 { 536 if(tile_pos_x == 0) 537 { /* Filling -1 in left column */ 538 pi4_tile_id_map_temp[-1] = -1; 539 } 540 541 for(ctb_col_ctr = 0; (ctb_col_ctr < tile_wd_in_ctb); ctb_col_ctr++) 542 { 543 pi4_tile_id_map_temp[ctb_col_ctr] = tile_ctr; 544 } 545 546 if(frame_width_in_ctb == (tile_pos_x + tile_wd_in_ctb)) 547 { /* Filling -1 in right column */ 548 pi4_tile_id_map_temp[tile_wd_in_ctb] = -1; 549 } 550 551 pi4_tile_id_map_temp += ps_frm_ctb_prms->i4_tile_id_ctb_map_stride; 552 } 553 } 554 555 return (void *)ps_tile_params_base; 556 } 557 558 /*! 559 ****************************************************************************** 560 * \if Function name : update_last_coded_cu_qp \endif 561 * 562 * \brief Update i1_last_cu_qp based on CTB's position in tile 563 * 564 * \param[in] pi1_top_last_cu_qp 565 * Pointer to the CTB row's Qp storage 566 * \param[in] i1_entropy_coding_sync_enabled_flag 567 * flag to indicate rate control mode 568 * \param[in] ps_frm_ctb_prms 569 * Frame ctb parameters 570 * \param[in] i1_frame_qp 571 * Frame qp 572 * \param[in] vert_ctr 573 * first CTB row of frame 574 * \param[in] ctb_ctr 575 * ct row count 576 * \param[out] pi1_last_cu_qp 577 * Qp of the last CU of previous CTB row 578 * 579 * \return 580 * None 581 * 582 * \author 583 * Ittiam 584 * 585 ***************************************************************************** 586 */ 587 void update_last_coded_cu_qp( 588 WORD8 *pi1_top_last_cu_qp, 589 WORD8 i1_entropy_coding_sync_enabled_flag, 590 frm_ctb_ctxt_t *ps_frm_ctb_prms, 591 WORD8 i1_frame_qp, 592 WORD32 vert_ctr, 593 WORD32 ctb_ctr, 594 WORD8 *pi1_last_cu_qp) 595 { 596 WORD32 i4_curr_ctb_tile_id, i4_left_ctb_tile_id, i4_top_ctb_tile_id; 597 WORD32 *pi4_tile_id_map_temp; 598 599 pi4_tile_id_map_temp = ps_frm_ctb_prms->pi4_tile_id_map + 600 vert_ctr * ps_frm_ctb_prms->i4_tile_id_ctb_map_stride + ctb_ctr; 601 602 i4_curr_ctb_tile_id = *(pi4_tile_id_map_temp); 603 i4_left_ctb_tile_id = *(pi4_tile_id_map_temp - 1); 604 i4_top_ctb_tile_id = *(pi4_tile_id_map_temp - ps_frm_ctb_prms->i4_tile_id_ctb_map_stride); 605 606 if(i4_curr_ctb_tile_id == i4_left_ctb_tile_id) 607 { 608 return; 609 } 610 else if(i4_curr_ctb_tile_id != i4_top_ctb_tile_id) 611 { /* First CTB of tile */ 612 *pi1_last_cu_qp = i1_frame_qp; 613 } 614 else 615 { /* First CTB of CTB-row */ 616 if(1 == i1_entropy_coding_sync_enabled_flag) 617 { 618 *pi1_last_cu_qp = i1_frame_qp; 619 } 620 else 621 { 622 *pi1_last_cu_qp = *(pi1_top_last_cu_qp); 623 } 624 } 625 } 626
