1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 //===----------------------------------------------------------------------===// 14 // Target-independent interfaces which we are implementing. 15 //===----------------------------------------------------------------------===// 16 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // AArch64 Subtarget features. 21 // 22 23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 24 "Enable ARMv8 FP">; 25 26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; 28 29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 30 "Enable cryptographic instructions">; 31 32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 33 "Enable ARMv8 CRC-32 checksum instructions">; 34 35 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 36 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; 37 38 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 39 "Enable ARMv8 PMUv3 Performance Monitors extension">; 40 41 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 42 "Full FP16", [FeatureFPARMv8]>; 43 44 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 45 "Enable Statistical Profiling extension">; 46 47 /// Cyclone has register move instructions which are "free". 48 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 49 "Has zero-cycle register moves">; 50 51 /// Cyclone has instructions which zero registers for "free". 52 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 53 "Has zero-cycle zeroing instructions">; 54 55 def FeatureStrictAlign : SubtargetFeature<"strict-align", 56 "StrictAlign", "true", 57 "Disallow all unaligned memory " 58 "access">; 59 60 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true", 61 "Reserve X18, making it unavailable " 62 "as a GPR">; 63 64 def FeatureMergeNarrowLd : SubtargetFeature<"merge-narrow-ld", 65 "MergeNarrowLoads", "true", 66 "Merge narrow load instructions">; 67 68 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 69 "Use alias analysis during codegen">; 70 71 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 72 "true", 73 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 74 75 def FeaturePredictableSelectIsExpensive : SubtargetFeature< 76 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 77 "Prefer likely predicted branches over selects">; 78 79 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 80 "CustomAsCheapAsMove", "true", 81 "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">; 82 83 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 84 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 85 86 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 87 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; 88 89 def FeatureAvoidQuadLdStPairs : SubtargetFeature<"no-quad-ldst-pairs", 90 "AvoidQuadLdStPairs", "true", 91 "Do not form quad load/store pair operations">; 92 93 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 94 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 95 "true", "Use alternative pattern for sextload convert to f32">; 96 97 def FeatureMacroOpFusion : SubtargetFeature< 98 "macroop-fusion", "HasMacroOpFusion", "true", 99 "CPU supports macro op fusion">; 100 101 def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 102 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 103 "Disable latency scheduling heuristic">; 104 105 def FeatureUseRSqrt : SubtargetFeature< 106 "use-reverse-square-root", "UseRSqrt", "true", "Use reverse square root">; 107 108 //===----------------------------------------------------------------------===// 109 // Architectures. 110 // 111 112 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 113 "Support ARM v8.1a instructions", [FeatureCRC]>; 114 115 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 116 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>; 117 118 //===----------------------------------------------------------------------===// 119 // Register File Description 120 //===----------------------------------------------------------------------===// 121 122 include "AArch64RegisterInfo.td" 123 include "AArch64CallingConvention.td" 124 125 //===----------------------------------------------------------------------===// 126 // Instruction Descriptions 127 //===----------------------------------------------------------------------===// 128 129 include "AArch64Schedule.td" 130 include "AArch64InstrInfo.td" 131 132 def AArch64InstrInfo : InstrInfo; 133 134 //===----------------------------------------------------------------------===// 135 // Named operands for MRS/MSR/TLBI/... 136 //===----------------------------------------------------------------------===// 137 138 include "AArch64SystemOperands.td" 139 140 //===----------------------------------------------------------------------===// 141 // AArch64 Processors supported. 142 // 143 include "AArch64SchedA53.td" 144 include "AArch64SchedA57.td" 145 include "AArch64SchedCyclone.td" 146 include "AArch64SchedM1.td" 147 include "AArch64SchedKryo.td" 148 include "AArch64SchedVulcan.td" 149 150 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 151 "Cortex-A35 ARM processors", [ 152 FeatureCRC, 153 FeatureCrypto, 154 FeatureFPARMv8, 155 FeatureNEON, 156 FeaturePerfMon 157 ]>; 158 159 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 160 "Cortex-A53 ARM processors", [ 161 FeatureBalanceFPOps, 162 FeatureCRC, 163 FeatureCrypto, 164 FeatureCustomCheapAsMoveHandling, 165 FeatureFPARMv8, 166 FeatureNEON, 167 FeaturePerfMon, 168 FeaturePostRAScheduler, 169 FeatureUseAA 170 ]>; 171 172 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 173 "Cortex-A57 ARM processors", [ 174 FeatureBalanceFPOps, 175 FeatureCRC, 176 FeatureCrypto, 177 FeatureCustomCheapAsMoveHandling, 178 FeatureFPARMv8, 179 FeatureMergeNarrowLd, 180 FeatureNEON, 181 FeaturePerfMon, 182 FeaturePostRAScheduler, 183 FeaturePredictableSelectIsExpensive 184 ]>; 185 186 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 187 "Cortex-A72 ARM processors", [ 188 FeatureCRC, 189 FeatureCrypto, 190 FeatureFPARMv8, 191 FeatureNEON, 192 FeaturePerfMon 193 ]>; 194 195 def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 196 "Cortex-A73 ARM processors", [ 197 FeatureCRC, 198 FeatureCrypto, 199 FeatureFPARMv8, 200 FeatureNEON, 201 FeaturePerfMon 202 ]>; 203 204 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", 205 "Cyclone", [ 206 FeatureAlternateSExtLoadCVTF32Pattern, 207 FeatureCrypto, 208 FeatureDisableLatencySchedHeuristic, 209 FeatureFPARMv8, 210 FeatureMacroOpFusion, 211 FeatureNEON, 212 FeaturePerfMon, 213 FeatureSlowMisaligned128Store, 214 FeatureZCRegMove, 215 FeatureZCZeroing 216 ]>; 217 218 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", 219 "Samsung Exynos-M1 processors", [ 220 FeatureAvoidQuadLdStPairs, 221 FeatureCRC, 222 FeatureCrypto, 223 FeatureCustomCheapAsMoveHandling, 224 FeatureFPARMv8, 225 FeatureNEON, 226 FeaturePerfMon, 227 FeaturePostRAScheduler, 228 FeatureUseRSqrt 229 ]>; 230 231 def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 232 "Qualcomm Kryo processors", [ 233 FeatureCRC, 234 FeatureCrypto, 235 FeatureCustomCheapAsMoveHandling, 236 FeatureFPARMv8, 237 FeatureMergeNarrowLd, 238 FeatureNEON, 239 FeaturePerfMon, 240 FeaturePostRAScheduler, 241 FeaturePredictableSelectIsExpensive, 242 FeatureZCZeroing 243 ]>; 244 245 def ProcVulcan : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan", 246 "Broadcom Vulcan processors", [ 247 FeatureCRC, 248 FeatureCrypto, 249 FeatureFPARMv8, 250 FeatureMacroOpFusion, 251 FeatureNEON, 252 FeaturePostRAScheduler, 253 HasV8_1aOps]>; 254 255 def : ProcessorModel<"generic", NoSchedModel, [ 256 FeatureCRC, 257 FeatureFPARMv8, 258 FeatureNEON, 259 FeaturePerfMon, 260 FeaturePostRAScheduler 261 ]>; 262 263 // FIXME: Cortex-A35 is currently modelled as a Cortex-A53 264 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; 265 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; 266 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; 267 // FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57. 268 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; 269 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; 270 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>; 271 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>; 272 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; 273 def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>; 274 275 //===----------------------------------------------------------------------===// 276 // Assembly parser 277 //===----------------------------------------------------------------------===// 278 279 def GenericAsmParserVariant : AsmParserVariant { 280 int Variant = 0; 281 string Name = "generic"; 282 string BreakCharacters = "."; 283 } 284 285 def AppleAsmParserVariant : AsmParserVariant { 286 int Variant = 1; 287 string Name = "apple-neon"; 288 string BreakCharacters = "."; 289 } 290 291 //===----------------------------------------------------------------------===// 292 // Assembly printer 293 //===----------------------------------------------------------------------===// 294 // AArch64 Uses the MC printer for asm output, so make sure the TableGen 295 // AsmWriter bits get associated with the correct class. 296 def GenericAsmWriter : AsmWriter { 297 string AsmWriterClassName = "InstPrinter"; 298 int PassSubtarget = 1; 299 int Variant = 0; 300 bit isMCAsmWriter = 1; 301 } 302 303 def AppleAsmWriter : AsmWriter { 304 let AsmWriterClassName = "AppleInstPrinter"; 305 int PassSubtarget = 1; 306 int Variant = 1; 307 int isMCAsmWriter = 1; 308 } 309 310 //===----------------------------------------------------------------------===// 311 // Target Declaration 312 //===----------------------------------------------------------------------===// 313 314 def AArch64 : Target { 315 let InstructionSet = AArch64InstrInfo; 316 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 317 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 318 } 319
