1 //==- AArch64SchedKryo.td - Qualcomm Kryo Scheduling Defs ---*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the machine model for Qualcomm Kryo to support 11 // instruction scheduling and other instruction cost heuristics. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // The issue width is set to five, matching the five issue queues for expanded 17 // uops. Now, the latency spreadsheet has information based on fragmented uops, 18 // but these do not actually take up an issue queue. 19 20 def KryoModel : SchedMachineModel { 21 let IssueWidth = 5; // 5-wide issue for expanded uops 22 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer 23 let LoadLatency = 4; // Optimistic load latency 24 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch 25 26 // Enable partial & runtime unrolling. The magic number is chosen based on 27 // experiments and benchmarking data. 28 let LoopMicroOpBufferSize = 16; 29 let CompleteModel = 1; 30 } 31 32 //===----------------------------------------------------------------------===// 33 // Define each kind of processor resource and number available on Kryo. 34 35 let SchedModel = KryoModel in { 36 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops 37 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops 38 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops 39 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops 40 def KryoUnitX : ProcResGroup<[KryoUnitXA, // Type X micro-ops 41 KryoUnitXB]>; 42 def KryoUnitY : ProcResGroup<[KryoUnitYA, // Type Y micro-ops 43 KryoUnitYB]>; 44 def KryoUnitXY : ProcResGroup<[KryoUnitXA, // Type XY micro-ops 45 KryoUnitXB, 46 KryoUnitYA, 47 KryoUnitYB]>; 48 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops 49 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops 50 def KryoUnitLS : ProcResGroup<[KryoUnitLSA, // Type LS micro-ops 51 KryoUnitLSB]>; 52 } 53 54 let SchedModel = KryoModel in { 55 56 //===----------------------------------------------------------------------===// 57 // Map the target-defined scheduler read/write resources and latency for 58 // Kryo. 59 60 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; } 61 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; } 62 def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]> 63 { let Latency = 2; let NumMicroOps = 2; } 64 def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]> 65 { let Latency = 2; let NumMicroOps = 2; } 66 def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]> 67 { let Latency = 2; let NumMicroOps = 2; } 68 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; } 69 def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]> 70 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1 71 def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]> 72 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1 73 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; } 74 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; } 75 def : WriteRes<WriteBr, [KryoUnitXY]> { let Latency = 1; } 76 def : WriteRes<WriteBrReg, [KryoUnitXY]> { let Latency = 1; } 77 def : WriteRes<WriteLD, [KryoUnitLS]> { let Latency = 4; } 78 def : WriteRes<WriteST, [KryoUnitLS]> { let Latency = 4; } 79 def : WriteRes<WriteSTP, [KryoUnitLS]> { let Latency = 4; } 80 def : WriteRes<WriteAdr, [KryoUnitXY]> { let Latency = 6; } 81 def : WriteRes<WriteLDIdx, [KryoUnitLS]> { let Latency = 4; } 82 def : WriteRes<WriteSTIdx, [KryoUnitLS]> { let Latency = 4; } 83 def : WriteRes<WriteF, [KryoUnitXY, KryoUnitXY]> 84 { let Latency = 3; let NumMicroOps = 2; } 85 def : WriteRes<WriteFCmp, [KryoUnitXY]> { let Latency = 2; } 86 def : WriteRes<WriteFCvt, [KryoUnitX]> { let Latency = 4; } 87 def : WriteRes<WriteFCopy, [KryoUnitXY]> { let Latency = 6; } 88 def : WriteRes<WriteFImm, [KryoUnitXY]> { let Latency = 6; } 89 def : WriteRes<WriteFMul, [KryoUnitX, KryoUnitX]> 90 { let Latency = 6; let NumMicroOps = 2; } 91 def : WriteRes<WriteFDiv, [KryoUnitXA, KryoUnitY]> 92 { let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1 93 def : WriteRes<WriteV, [KryoUnitXY]> { let Latency = 6; } 94 def : WriteRes<WriteVLD, [KryoUnitLS]> { let Latency = 4; } 95 def : WriteRes<WriteVST, [KryoUnitLS]> { let Latency = 4; } 96 97 def : WriteRes<WriteSys, []> { let Latency = 1; } 98 def : WriteRes<WriteBarrier, []> { let Latency = 1; } 99 def : WriteRes<WriteHint, []> { let Latency = 1; } 100 101 def : WriteRes<WriteLDHi, []> { let Latency = 4; } 102 103 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 104 105 // No forwarding logic is modelled yet. 106 def : ReadAdvance<ReadI, 0>; 107 def : ReadAdvance<ReadISReg, 0>; 108 def : ReadAdvance<ReadIEReg, 0>; 109 def : ReadAdvance<ReadIM, 0>; 110 def : ReadAdvance<ReadIMA, 0>; 111 def : ReadAdvance<ReadID, 0>; 112 def : ReadAdvance<ReadExtrHi, 0>; 113 def : ReadAdvance<ReadAdrBase, 0>; 114 def : ReadAdvance<ReadVLD, 0>; 115 116 117 //===----------------------------------------------------------------------===// 118 // Specialize the coarse model by associating instruction groups with the 119 // subtarget-defined types. As the modeled is refined, this will override most 120 // of the above SchedWriteRes and SchedAlias mappings. 121 122 // Miscellaneous 123 // ----------------------------------------------------------------------------- 124 125 def : InstRW<[WriteI], (instrs COPY)>; 126 127 128 // Detailed Refinedments 129 // ----------------------------------------------------------------------------- 130 include "AArch64SchedKryoDetails.td" 131 132 133 } // SchedModel = KryoModel 134
