1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // R600 Instruction format definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class InstR600 <dag outs, dag ins, string asm, list<dag> pattern, 15 InstrItinClass itin> 16 : AMDGPUInst <outs, ins, asm, pattern> { 17 18 field bits<64> Inst; 19 bit Trig = 0; 20 bit Op3 = 0; 21 bit isVector = 0; 22 bits<2> FlagOperandIdx = 0; 23 bit Op1 = 0; 24 bit Op2 = 0; 25 bit LDS_1A = 0; 26 bit LDS_1A1D = 0; 27 bit HasNativeOperands = 0; 28 bit VTXInst = 0; 29 bit TEXInst = 0; 30 bit ALUInst = 0; 31 bit IsExport = 0; 32 bit LDS_1A2D = 0; 33 34 let Namespace = "AMDGPU"; 35 let OutOperandList = outs; 36 let InOperandList = ins; 37 let AsmString = asm; 38 let Pattern = pattern; 39 let Itinerary = itin; 40 41 // No AsmMatcher support. 42 let isCodeGenOnly = 1; 43 44 let TSFlags{4} = Trig; 45 let TSFlags{5} = Op3; 46 47 // Vector instructions are instructions that must fill all slots in an 48 // instruction group 49 let TSFlags{6} = isVector; 50 let TSFlags{8-7} = FlagOperandIdx; 51 let TSFlags{9} = HasNativeOperands; 52 let TSFlags{10} = Op1; 53 let TSFlags{11} = Op2; 54 let TSFlags{12} = VTXInst; 55 let TSFlags{13} = TEXInst; 56 let TSFlags{14} = ALUInst; 57 let TSFlags{15} = LDS_1A; 58 let TSFlags{16} = LDS_1A1D; 59 let TSFlags{17} = IsExport; 60 let TSFlags{18} = LDS_1A2D; 61 } 62 63 //===----------------------------------------------------------------------===// 64 // ALU instructions 65 //===----------------------------------------------------------------------===// 66 67 class R600_ALU_LDS_Word0 { 68 field bits<32> Word0; 69 70 bits<11> src0; 71 bits<1> src0_rel; 72 bits<11> src1; 73 bits<1> src1_rel; 74 bits<3> index_mode = 0; 75 bits<2> pred_sel; 76 bits<1> last; 77 78 bits<9> src0_sel = src0{8-0}; 79 bits<2> src0_chan = src0{10-9}; 80 bits<9> src1_sel = src1{8-0}; 81 bits<2> src1_chan = src1{10-9}; 82 83 let Word0{8-0} = src0_sel; 84 let Word0{9} = src0_rel; 85 let Word0{11-10} = src0_chan; 86 let Word0{21-13} = src1_sel; 87 let Word0{22} = src1_rel; 88 let Word0{24-23} = src1_chan; 89 let Word0{28-26} = index_mode; 90 let Word0{30-29} = pred_sel; 91 let Word0{31} = last; 92 } 93 94 class R600ALU_Word0 : R600_ALU_LDS_Word0 { 95 96 bits<1> src0_neg; 97 bits<1> src1_neg; 98 99 let Word0{12} = src0_neg; 100 let Word0{25} = src1_neg; 101 } 102 103 class R600ALU_Word1 { 104 field bits<32> Word1; 105 106 bits<11> dst; 107 bits<3> bank_swizzle; 108 bits<1> dst_rel; 109 bits<1> clamp; 110 111 bits<7> dst_sel = dst{6-0}; 112 bits<2> dst_chan = dst{10-9}; 113 114 let Word1{20-18} = bank_swizzle; 115 let Word1{27-21} = dst_sel; 116 let Word1{28} = dst_rel; 117 let Word1{30-29} = dst_chan; 118 let Word1{31} = clamp; 119 } 120 121 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{ 122 123 bits<1> src0_abs; 124 bits<1> src1_abs; 125 bits<1> update_exec_mask; 126 bits<1> update_pred; 127 bits<1> write; 128 bits<2> omod; 129 130 let Word1{0} = src0_abs; 131 let Word1{1} = src1_abs; 132 let Word1{2} = update_exec_mask; 133 let Word1{3} = update_pred; 134 let Word1{4} = write; 135 let Word1{6-5} = omod; 136 let Word1{17-7} = alu_inst; 137 } 138 139 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{ 140 141 bits<11> src2; 142 bits<1> src2_rel; 143 bits<1> src2_neg; 144 145 bits<9> src2_sel = src2{8-0}; 146 bits<2> src2_chan = src2{10-9}; 147 148 let Word1{8-0} = src2_sel; 149 let Word1{9} = src2_rel; 150 let Word1{11-10} = src2_chan; 151 let Word1{12} = src2_neg; 152 let Word1{17-13} = alu_inst; 153 } 154 155 class R600LDS_Word1 { 156 field bits<32> Word1; 157 158 bits<11> src2; 159 bits<9> src2_sel = src2{8-0}; 160 bits<2> src2_chan = src2{10-9}; 161 bits<1> src2_rel; 162 // offset specifies the stride offset to the second set of data to be read 163 // from. This is a dword offset. 164 bits<5> alu_inst = 17; // OP3_INST_LDS_IDX_OP 165 bits<3> bank_swizzle; 166 bits<6> lds_op; 167 bits<2> dst_chan = 0; 168 169 let Word1{8-0} = src2_sel; 170 let Word1{9} = src2_rel; 171 let Word1{11-10} = src2_chan; 172 let Word1{17-13} = alu_inst; 173 let Word1{20-18} = bank_swizzle; 174 let Word1{26-21} = lds_op; 175 let Word1{30-29} = dst_chan; 176 } 177 178 179 /* 180 XXX: R600 subtarget uses a slightly different encoding than the other 181 subtargets. We currently handle this in R600MCCodeEmitter, but we may 182 want to use these instruction classes in the future. 183 184 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 { 185 186 bits<1> fog_merge; 187 bits<10> alu_inst; 188 189 let Inst{37} = fog_merge; 190 let Inst{39-38} = omod; 191 let Inst{49-40} = alu_inst; 192 } 193 194 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 { 195 196 bits<11> alu_inst; 197 198 let Inst{38-37} = omod; 199 let Inst{49-39} = alu_inst; 200 } 201 */ 202 203 //===----------------------------------------------------------------------===// 204 // Vertex Fetch instructions 205 //===----------------------------------------------------------------------===// 206 207 class VTX_WORD0 { 208 field bits<32> Word0; 209 bits<7> src_gpr; 210 bits<5> VC_INST; 211 bits<2> FETCH_TYPE; 212 bits<1> FETCH_WHOLE_QUAD; 213 bits<8> BUFFER_ID; 214 bits<1> SRC_REL; 215 bits<2> SRC_SEL_X; 216 217 let Word0{4-0} = VC_INST; 218 let Word0{6-5} = FETCH_TYPE; 219 let Word0{7} = FETCH_WHOLE_QUAD; 220 let Word0{15-8} = BUFFER_ID; 221 let Word0{22-16} = src_gpr; 222 let Word0{23} = SRC_REL; 223 let Word0{25-24} = SRC_SEL_X; 224 } 225 226 class VTX_WORD0_eg : VTX_WORD0 { 227 228 bits<6> MEGA_FETCH_COUNT; 229 230 let Word0{31-26} = MEGA_FETCH_COUNT; 231 } 232 233 class VTX_WORD0_cm : VTX_WORD0 { 234 235 bits<2> SRC_SEL_Y; 236 bits<2> STRUCTURED_READ; 237 bits<1> LDS_REQ; 238 bits<1> COALESCED_READ; 239 240 let Word0{27-26} = SRC_SEL_Y; 241 let Word0{29-28} = STRUCTURED_READ; 242 let Word0{30} = LDS_REQ; 243 let Word0{31} = COALESCED_READ; 244 } 245 246 class VTX_WORD1_GPR { 247 field bits<32> Word1; 248 bits<7> dst_gpr; 249 bits<1> DST_REL; 250 bits<3> DST_SEL_X; 251 bits<3> DST_SEL_Y; 252 bits<3> DST_SEL_Z; 253 bits<3> DST_SEL_W; 254 bits<1> USE_CONST_FIELDS; 255 bits<6> DATA_FORMAT; 256 bits<2> NUM_FORMAT_ALL; 257 bits<1> FORMAT_COMP_ALL; 258 bits<1> SRF_MODE_ALL; 259 260 let Word1{6-0} = dst_gpr; 261 let Word1{7} = DST_REL; 262 let Word1{8} = 0; // Reserved 263 let Word1{11-9} = DST_SEL_X; 264 let Word1{14-12} = DST_SEL_Y; 265 let Word1{17-15} = DST_SEL_Z; 266 let Word1{20-18} = DST_SEL_W; 267 let Word1{21} = USE_CONST_FIELDS; 268 let Word1{27-22} = DATA_FORMAT; 269 let Word1{29-28} = NUM_FORMAT_ALL; 270 let Word1{30} = FORMAT_COMP_ALL; 271 let Word1{31} = SRF_MODE_ALL; 272 } 273 274 //===----------------------------------------------------------------------===// 275 // Texture fetch instructions 276 //===----------------------------------------------------------------------===// 277 278 class TEX_WORD0 { 279 field bits<32> Word0; 280 281 bits<5> TEX_INST; 282 bits<2> INST_MOD; 283 bits<1> FETCH_WHOLE_QUAD; 284 bits<8> RESOURCE_ID; 285 bits<7> SRC_GPR; 286 bits<1> SRC_REL; 287 bits<1> ALT_CONST; 288 bits<2> RESOURCE_INDEX_MODE; 289 bits<2> SAMPLER_INDEX_MODE; 290 291 let Word0{4-0} = TEX_INST; 292 let Word0{6-5} = INST_MOD; 293 let Word0{7} = FETCH_WHOLE_QUAD; 294 let Word0{15-8} = RESOURCE_ID; 295 let Word0{22-16} = SRC_GPR; 296 let Word0{23} = SRC_REL; 297 let Word0{24} = ALT_CONST; 298 let Word0{26-25} = RESOURCE_INDEX_MODE; 299 let Word0{28-27} = SAMPLER_INDEX_MODE; 300 } 301 302 class TEX_WORD1 { 303 field bits<32> Word1; 304 305 bits<7> DST_GPR; 306 bits<1> DST_REL; 307 bits<3> DST_SEL_X; 308 bits<3> DST_SEL_Y; 309 bits<3> DST_SEL_Z; 310 bits<3> DST_SEL_W; 311 bits<7> LOD_BIAS; 312 bits<1> COORD_TYPE_X; 313 bits<1> COORD_TYPE_Y; 314 bits<1> COORD_TYPE_Z; 315 bits<1> COORD_TYPE_W; 316 317 let Word1{6-0} = DST_GPR; 318 let Word1{7} = DST_REL; 319 let Word1{11-9} = DST_SEL_X; 320 let Word1{14-12} = DST_SEL_Y; 321 let Word1{17-15} = DST_SEL_Z; 322 let Word1{20-18} = DST_SEL_W; 323 let Word1{27-21} = LOD_BIAS; 324 let Word1{28} = COORD_TYPE_X; 325 let Word1{29} = COORD_TYPE_Y; 326 let Word1{30} = COORD_TYPE_Z; 327 let Word1{31} = COORD_TYPE_W; 328 } 329 330 class TEX_WORD2 { 331 field bits<32> Word2; 332 333 bits<5> OFFSET_X; 334 bits<5> OFFSET_Y; 335 bits<5> OFFSET_Z; 336 bits<5> SAMPLER_ID; 337 bits<3> SRC_SEL_X; 338 bits<3> SRC_SEL_Y; 339 bits<3> SRC_SEL_Z; 340 bits<3> SRC_SEL_W; 341 342 let Word2{4-0} = OFFSET_X; 343 let Word2{9-5} = OFFSET_Y; 344 let Word2{14-10} = OFFSET_Z; 345 let Word2{19-15} = SAMPLER_ID; 346 let Word2{22-20} = SRC_SEL_X; 347 let Word2{25-23} = SRC_SEL_Y; 348 let Word2{28-26} = SRC_SEL_Z; 349 let Word2{31-29} = SRC_SEL_W; 350 } 351 352 //===----------------------------------------------------------------------===// 353 // Control Flow Instructions 354 //===----------------------------------------------------------------------===// 355 356 class CF_WORD1_R600 { 357 field bits<32> Word1; 358 359 bits<3> POP_COUNT; 360 bits<5> CF_CONST; 361 bits<2> COND; 362 bits<3> COUNT; 363 bits<6> CALL_COUNT; 364 bits<1> COUNT_3; 365 bits<1> END_OF_PROGRAM; 366 bits<1> VALID_PIXEL_MODE; 367 bits<7> CF_INST; 368 bits<1> WHOLE_QUAD_MODE; 369 bits<1> BARRIER; 370 371 let Word1{2-0} = POP_COUNT; 372 let Word1{7-3} = CF_CONST; 373 let Word1{9-8} = COND; 374 let Word1{12-10} = COUNT; 375 let Word1{18-13} = CALL_COUNT; 376 let Word1{19} = COUNT_3; 377 let Word1{21} = END_OF_PROGRAM; 378 let Word1{22} = VALID_PIXEL_MODE; 379 let Word1{29-23} = CF_INST; 380 let Word1{30} = WHOLE_QUAD_MODE; 381 let Word1{31} = BARRIER; 382 } 383 384 class CF_WORD0_EG { 385 field bits<32> Word0; 386 387 bits<24> ADDR; 388 bits<3> JUMPTABLE_SEL; 389 390 let Word0{23-0} = ADDR; 391 let Word0{26-24} = JUMPTABLE_SEL; 392 } 393 394 class CF_WORD1_EG { 395 field bits<32> Word1; 396 397 bits<3> POP_COUNT; 398 bits<5> CF_CONST; 399 bits<2> COND; 400 bits<6> COUNT; 401 bits<1> VALID_PIXEL_MODE; 402 bits<1> END_OF_PROGRAM; 403 bits<8> CF_INST; 404 bits<1> BARRIER; 405 406 let Word1{2-0} = POP_COUNT; 407 let Word1{7-3} = CF_CONST; 408 let Word1{9-8} = COND; 409 let Word1{15-10} = COUNT; 410 let Word1{20} = VALID_PIXEL_MODE; 411 let Word1{21} = END_OF_PROGRAM; 412 let Word1{29-22} = CF_INST; 413 let Word1{31} = BARRIER; 414 } 415 416 class CF_ALU_WORD0 { 417 field bits<32> Word0; 418 419 bits<22> ADDR; 420 bits<4> KCACHE_BANK0; 421 bits<4> KCACHE_BANK1; 422 bits<2> KCACHE_MODE0; 423 424 let Word0{21-0} = ADDR; 425 let Word0{25-22} = KCACHE_BANK0; 426 let Word0{29-26} = KCACHE_BANK1; 427 let Word0{31-30} = KCACHE_MODE0; 428 } 429 430 class CF_ALU_WORD1 { 431 field bits<32> Word1; 432 433 bits<2> KCACHE_MODE1; 434 bits<8> KCACHE_ADDR0; 435 bits<8> KCACHE_ADDR1; 436 bits<7> COUNT; 437 bits<1> ALT_CONST; 438 bits<4> CF_INST; 439 bits<1> WHOLE_QUAD_MODE; 440 bits<1> BARRIER; 441 442 let Word1{1-0} = KCACHE_MODE1; 443 let Word1{9-2} = KCACHE_ADDR0; 444 let Word1{17-10} = KCACHE_ADDR1; 445 let Word1{24-18} = COUNT; 446 let Word1{25} = ALT_CONST; 447 let Word1{29-26} = CF_INST; 448 let Word1{30} = WHOLE_QUAD_MODE; 449 let Word1{31} = BARRIER; 450 } 451 452 class CF_ALLOC_EXPORT_WORD0_RAT { 453 field bits<32> Word0; 454 455 bits<4> rat_id; 456 bits<6> rat_inst; 457 bits<2> rim; 458 bits<2> type; 459 bits<7> rw_gpr; 460 bits<1> rw_rel; 461 bits<7> index_gpr; 462 bits<2> elem_size; 463 464 let Word0{3-0} = rat_id; 465 let Word0{9-4} = rat_inst; 466 let Word0{10} = 0; // Reserved 467 let Word0{12-11} = rim; 468 let Word0{14-13} = type; 469 let Word0{21-15} = rw_gpr; 470 let Word0{22} = rw_rel; 471 let Word0{29-23} = index_gpr; 472 let Word0{31-30} = elem_size; 473 } 474 475 class CF_ALLOC_EXPORT_WORD1_BUF { 476 field bits<32> Word1; 477 478 bits<12> array_size; 479 bits<4> comp_mask; 480 bits<4> burst_count; 481 bits<1> vpm; 482 bits<1> eop; 483 bits<8> cf_inst; 484 bits<1> mark; 485 bits<1> barrier; 486 487 let Word1{11-0} = array_size; 488 let Word1{15-12} = comp_mask; 489 let Word1{19-16} = burst_count; 490 let Word1{20} = vpm; 491 let Word1{21} = eop; 492 let Word1{29-22} = cf_inst; 493 let Word1{30} = mark; 494 let Word1{31} = barrier; 495 } 496
