1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Thumb instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Thumb specific DAG Nodes. 16 // 17 18 def imm_sr_XFORM: SDNodeXForm<imm, [{ 19 unsigned Imm = N->getZExtValue(); 20 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32); 21 }]>; 22 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 23 def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 24 uint64_t Imm = N->getZExtValue(); 25 return Imm > 0 && Imm <= 32; 26 }], imm_sr_XFORM> { 27 let PrintMethod = "printThumbSRImm"; 28 let ParserMatchClass = ThumbSRImmAsmOperand; 29 } 30 31 def imm_comp_XFORM : SDNodeXForm<imm, [{ 32 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), 33 MVT::i32); 34 }]>; 35 36 def imm0_7_neg : PatLeaf<(i32 imm), [{ 37 return (uint32_t)-N->getZExtValue() < 8; 38 }], imm_neg_XFORM>; 39 40 def imm0_255_comp : PatLeaf<(i32 imm), [{ 41 return ~((uint32_t)N->getZExtValue()) < 256; 42 }]>; 43 44 def imm8_255 : ImmLeaf<i32, [{ 45 return Imm >= 8 && Imm < 256; 46 }]>; 47 def imm8_255_neg : PatLeaf<(i32 imm), [{ 48 unsigned Val = -N->getZExtValue(); 49 return Val >= 8 && Val < 256; 50 }], imm_neg_XFORM>; 51 52 // Break imm's up into two pieces: an immediate + a left shift. This uses 53 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 54 // to get the val/shift pieces. 55 def thumb_immshifted : PatLeaf<(imm), [{ 56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 57 }]>; 58 59 def thumb_immshifted_val : SDNodeXForm<imm, [{ 60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 61 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 62 }]>; 63 64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 66 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32); 67 }]>; 68 69 def imm256_510 : ImmLeaf<i32, [{ 70 return Imm >= 256 && Imm < 511; 71 }]>; 72 73 def thumb_imm256_510_addend : SDNodeXForm<imm, [{ 74 return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32); 75 }]>; 76 77 // Scaled 4 immediate. 78 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 79 def t_imm0_1020s4 : Operand<i32> { 80 let PrintMethod = "printThumbS4ImmOperand"; 81 let ParserMatchClass = t_imm0_1020s4_asmoperand; 82 let OperandType = "OPERAND_IMMEDIATE"; 83 } 84 85 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 86 def t_imm0_508s4 : Operand<i32> { 87 let PrintMethod = "printThumbS4ImmOperand"; 88 let ParserMatchClass = t_imm0_508s4_asmoperand; 89 let OperandType = "OPERAND_IMMEDIATE"; 90 } 91 // Alias use only, so no printer is necessary. 92 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 93 def t_imm0_508s4_neg : Operand<i32> { 94 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 95 let OperandType = "OPERAND_IMMEDIATE"; 96 } 97 98 // Define Thumb specific addressing modes. 99 100 // unsigned 8-bit, 2-scaled memory offset 101 class OperandUnsignedOffset_b8s2 : AsmOperandClass { 102 let Name = "UnsignedOffset_b8s2"; 103 let PredicateMethod = "isUnsignedOffset<8, 2>"; 104 } 105 106 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 107 108 // thumb style PC relative operand. signed, 8 bits magnitude, 109 // two bits shift. can be represented as either [pc, #imm], #imm, 110 // or relocatable expression... 111 def ThumbMemPC : AsmOperandClass { 112 let Name = "ThumbMemPC"; 113 } 114 115 let OperandType = "OPERAND_PCREL" in { 116 def t_brtarget : Operand<OtherVT> { 117 let EncoderMethod = "getThumbBRTargetOpValue"; 118 let DecoderMethod = "DecodeThumbBROperand"; 119 } 120 121 // ADR instruction labels. 122 def t_adrlabel : Operand<i32> { 123 let EncoderMethod = "getThumbAdrLabelOpValue"; 124 let PrintMethod = "printAdrLabelOperand<2>"; 125 let ParserMatchClass = UnsignedOffset_b8s2; 126 } 127 128 129 def thumb_br_target : Operand<OtherVT> { 130 let ParserMatchClass = ThumbBranchTarget; 131 let EncoderMethod = "getThumbBranchTargetOpValue"; 132 let OperandType = "OPERAND_PCREL"; 133 } 134 135 def thumb_bl_target : Operand<i32> { 136 let ParserMatchClass = ThumbBranchTarget; 137 let EncoderMethod = "getThumbBLTargetOpValue"; 138 let DecoderMethod = "DecodeThumbBLTargetOperand"; 139 } 140 141 // Target for BLX *from* thumb mode. 142 def thumb_blx_target : Operand<i32> { 143 let ParserMatchClass = ARMBranchTarget; 144 let EncoderMethod = "getThumbBLXTargetOpValue"; 145 let DecoderMethod = "DecodeThumbBLXOffset"; 146 } 147 148 def thumb_bcc_target : Operand<OtherVT> { 149 let ParserMatchClass = ThumbBranchTarget; 150 let EncoderMethod = "getThumbBCCTargetOpValue"; 151 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 152 } 153 154 def thumb_cb_target : Operand<OtherVT> { 155 let ParserMatchClass = ThumbBranchTarget; 156 let EncoderMethod = "getThumbCBTargetOpValue"; 157 let DecoderMethod = "DecodeThumbCmpBROperand"; 158 } 159 160 // t_addrmode_pc := <label> => pc + imm8 * 4 161 // 162 def t_addrmode_pc : MemOperand { 163 let EncoderMethod = "getAddrModePCOpValue"; 164 let DecoderMethod = "DecodeThumbAddrModePC"; 165 let PrintMethod = "printThumbLdrLabelOperand"; 166 let ParserMatchClass = ThumbMemPC; 167 } 168 } 169 170 // t_addrmode_rr := reg + reg 171 // 172 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 173 def t_addrmode_rr : MemOperand, 174 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 175 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 176 let PrintMethod = "printThumbAddrModeRROperand"; 177 let DecoderMethod = "DecodeThumbAddrModeRR"; 178 let ParserMatchClass = t_addrmode_rr_asm_operand; 179 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 180 } 181 182 // t_addrmode_rrs := reg + reg 183 // 184 // We use separate scaled versions because the Select* functions need 185 // to explicitly check for a matching constant and return false here so that 186 // the reg+imm forms will match instead. This is a horrible way to do that, 187 // as it forces tight coupling between the methods, but it's how selectiondag 188 // currently works. 189 def t_addrmode_rrs1 : MemOperand, 190 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 191 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 192 let PrintMethod = "printThumbAddrModeRROperand"; 193 let DecoderMethod = "DecodeThumbAddrModeRR"; 194 let ParserMatchClass = t_addrmode_rr_asm_operand; 195 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 196 } 197 def t_addrmode_rrs2 : MemOperand, 198 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 199 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 200 let DecoderMethod = "DecodeThumbAddrModeRR"; 201 let PrintMethod = "printThumbAddrModeRROperand"; 202 let ParserMatchClass = t_addrmode_rr_asm_operand; 203 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 204 } 205 def t_addrmode_rrs4 : MemOperand, 206 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 207 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 208 let DecoderMethod = "DecodeThumbAddrModeRR"; 209 let PrintMethod = "printThumbAddrModeRROperand"; 210 let ParserMatchClass = t_addrmode_rr_asm_operand; 211 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 212 } 213 214 // t_addrmode_is4 := reg + imm5 * 4 215 // 216 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 217 def t_addrmode_is4 : MemOperand, 218 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 219 let EncoderMethod = "getAddrModeISOpValue"; 220 let DecoderMethod = "DecodeThumbAddrModeIS"; 221 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 222 let ParserMatchClass = t_addrmode_is4_asm_operand; 223 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 224 } 225 226 // t_addrmode_is2 := reg + imm5 * 2 227 // 228 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 229 def t_addrmode_is2 : MemOperand, 230 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 231 let EncoderMethod = "getAddrModeISOpValue"; 232 let DecoderMethod = "DecodeThumbAddrModeIS"; 233 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 234 let ParserMatchClass = t_addrmode_is2_asm_operand; 235 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 236 } 237 238 // t_addrmode_is1 := reg + imm5 239 // 240 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 241 def t_addrmode_is1 : MemOperand, 242 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 243 let EncoderMethod = "getAddrModeISOpValue"; 244 let DecoderMethod = "DecodeThumbAddrModeIS"; 245 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 246 let ParserMatchClass = t_addrmode_is1_asm_operand; 247 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 248 } 249 250 // t_addrmode_sp := sp + imm8 * 4 251 // 252 // FIXME: This really shouldn't have an explicit SP operand at all. It should 253 // be implicit, just like in the instruction encoding itself. 254 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 255 def t_addrmode_sp : MemOperand, 256 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 257 let EncoderMethod = "getAddrModeThumbSPOpValue"; 258 let DecoderMethod = "DecodeThumbAddrModeSP"; 259 let PrintMethod = "printThumbAddrModeSPOperand"; 260 let ParserMatchClass = t_addrmode_sp_asm_operand; 261 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 262 } 263 264 //===----------------------------------------------------------------------===// 265 // Miscellaneous Instructions. 266 // 267 268 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 269 // from removing one half of the matched pairs. That breaks PEI, which assumes 270 // these will always be in pairs, and asserts if it finds otherwise. Better way? 271 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 272 def tADJCALLSTACKUP : 273 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 274 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 275 Requires<[IsThumb, IsThumb1Only]>; 276 277 def tADJCALLSTACKDOWN : 278 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 279 [(ARMcallseq_start imm:$amt)]>, 280 Requires<[IsThumb, IsThumb1Only]>; 281 } 282 283 class T1SystemEncoding<bits<8> opc> 284 : T1Encoding<0b101111> { 285 let Inst{9-8} = 0b11; 286 let Inst{7-0} = opc; 287 } 288 289 def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", 290 [(int_arm_hint imm0_15:$imm)]>, 291 T1SystemEncoding<0x00>, 292 Requires<[IsThumb, HasV6M]> { 293 bits<4> imm; 294 let Inst{7-4} = imm; 295 } 296 297 // Note: When EmitPriority == 1, the alias will be used for printing 298 class tHintAlias<string Asm, dag Result, bit EmitPriority = 0> : tInstAlias<Asm, Result, EmitPriority> { 299 let Predicates = [IsThumb, HasV6M]; 300 } 301 302 def : tHintAlias<"nop$p", (tHINT 0, pred:$p), 1>; // A8.6.110 303 def : tHintAlias<"yield$p", (tHINT 1, pred:$p), 1>; // A8.6.410 304 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p), 1>; // A8.6.408 305 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409 306 def : tHintAlias<"sev$p", (tHINT 4, pred:$p), 1>; // A8.6.157 307 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p), 1> { 308 let Predicates = [IsThumb2, HasV8]; 309 } 310 311 // The imm operand $val can be used by a debugger to store more information 312 // about the breakpoint. 313 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 314 []>, 315 T1Encoding<0b101111> { 316 let Inst{9-8} = 0b10; 317 // A8.6.22 318 bits<8> val; 319 let Inst{7-0} = val; 320 } 321 // default immediate for breakpoint mnemonic 322 def : InstAlias<"bkpt", (tBKPT 0), 0>, Requires<[IsThumb]>; 323 324 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", 325 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { 326 let Inst{9-6} = 0b1010; 327 bits<6> val; 328 let Inst{5-0} = val; 329 } 330 331 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 332 []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> { 333 bits<1> end; 334 // A8.6.156 335 let Inst{9-5} = 0b10010; 336 let Inst{4} = 1; 337 let Inst{3} = end; 338 let Inst{2-0} = 0b000; 339 } 340 341 // Change Processor State is a system instruction -- for disassembly only. 342 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 343 NoItinerary, "cps$imod $iflags", []>, 344 T1Misc<0b0110011> { 345 // A8.6.38 & B6.1.1 346 bit imod; 347 bits<3> iflags; 348 349 let Inst{4} = imod; 350 let Inst{3} = 0; 351 let Inst{2-0} = iflags; 352 let DecoderMethod = "DecodeThumbCPS"; 353 } 354 355 // For both thumb1 and thumb2. 356 let isNotDuplicable = 1, isCodeGenOnly = 1 in 357 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 358 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 359 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 360 // A8.6.6 361 bits<3> dst; 362 let Inst{6-3} = 0b1111; // Rm = pc 363 let Inst{2-0} = dst; 364 } 365 366 // ADD <Rd>, sp, #<imm8> 367 // FIXME: This should not be marked as having side effects, and it should be 368 // rematerializable. Clearing the side effect bit causes miscompilations, 369 // probably because the instruction can be moved around. 370 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 371 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 372 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 373 // A6.2 & A8.6.8 374 bits<3> dst; 375 bits<8> imm; 376 let Inst{10-8} = dst; 377 let Inst{7-0} = imm; 378 let DecoderMethod = "DecodeThumbAddSpecialReg"; 379 } 380 381 // Thumb1 frame lowering is rather fragile, we hope to be able to use 382 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR. 383 def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset), 384 NoItinerary, []>, 385 Requires<[IsThumb, IsThumb1Only]> { 386 let Defs = [CPSR]; 387 } 388 389 // ADD sp, sp, #<imm7> 390 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 391 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 392 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 393 // A6.2.5 & A8.6.8 394 bits<7> imm; 395 let Inst{6-0} = imm; 396 let DecoderMethod = "DecodeThumbAddSPImm"; 397 } 398 399 // SUB sp, sp, #<imm7> 400 // FIXME: The encoding and the ASM string don't match up. 401 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 402 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 403 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 404 // A6.2.5 & A8.6.214 405 bits<7> imm; 406 let Inst{6-0} = imm; 407 let DecoderMethod = "DecodeThumbAddSPImm"; 408 } 409 410 def : tInstAlias<"add${p} sp, $imm", 411 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 412 def : tInstAlias<"add${p} sp, sp, $imm", 413 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 414 415 // Can optionally specify SP as a three operand instruction. 416 def : tInstAlias<"add${p} sp, sp, $imm", 417 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 418 def : tInstAlias<"sub${p} sp, sp, $imm", 419 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 420 421 // ADD <Rm>, sp 422 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 423 "add", "\t$Rdn, $sp, $Rn", []>, 424 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 425 // A8.6.9 Encoding T1 426 bits<4> Rdn; 427 let Inst{7} = Rdn{3}; 428 let Inst{6-3} = 0b1101; 429 let Inst{2-0} = Rdn{2-0}; 430 let DecoderMethod = "DecodeThumbAddSPReg"; 431 } 432 433 // ADD sp, <Rm> 434 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 435 "add", "\t$Rdn, $Rm", []>, 436 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 437 // A8.6.9 Encoding T2 438 bits<4> Rm; 439 let Inst{7} = 1; 440 let Inst{6-3} = Rm; 441 let Inst{2-0} = 0b101; 442 let DecoderMethod = "DecodeThumbAddSPReg"; 443 } 444 445 //===----------------------------------------------------------------------===// 446 // Control Flow Instructions. 447 // 448 449 // Indirect branches 450 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 451 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 452 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 453 // A6.2.3 & A8.6.25 454 bits<4> Rm; 455 let Inst{6-3} = Rm; 456 let Inst{2-0} = 0b000; 457 let Unpredictable{2-0} = 0b111; 458 } 459 def tBXNS : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bxns${p}\t$Rm", []>, 460 Requires<[IsThumb, Has8MSecExt]>, 461 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 462 bits<4> Rm; 463 let Inst{6-3} = Rm; 464 let Inst{2-0} = 0b100; 465 let Unpredictable{1-0} = 0b11; 466 } 467 } 468 469 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 470 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 471 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 472 473 // Alternative return instruction used by vararg functions. 474 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 475 2, IIC_Br, [], 476 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 477 } 478 479 // All calls clobber the non-callee saved registers. SP is marked as a use to 480 // prevent stack-pointer assignments that appear immediately before calls from 481 // potentially appearing dead. 482 let isCall = 1, 483 Defs = [LR], Uses = [SP] in { 484 // Also used for Thumb2 485 def tBL : TIx2<0b11110, 0b11, 1, 486 (outs), (ins pred:$p, thumb_bl_target:$func), IIC_Br, 487 "bl${p}\t$func", 488 [(ARMcall tglobaladdr:$func)]>, 489 Requires<[IsThumb]>, Sched<[WriteBrL]> { 490 bits<24> func; 491 let Inst{26} = func{23}; 492 let Inst{25-16} = func{20-11}; 493 let Inst{13} = func{22}; 494 let Inst{11} = func{21}; 495 let Inst{10-0} = func{10-0}; 496 } 497 498 // ARMv5T and above, also used for Thumb2 499 def tBLXi : TIx2<0b11110, 0b11, 0, 500 (outs), (ins pred:$p, thumb_blx_target:$func), IIC_Br, 501 "blx${p}\t$func", []>, 502 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> { 503 bits<24> func; 504 let Inst{26} = func{23}; 505 let Inst{25-16} = func{20-11}; 506 let Inst{13} = func{22}; 507 let Inst{11} = func{21}; 508 let Inst{10-1} = func{10-1}; 509 let Inst{0} = 0; // func{0} is assumed zero 510 } 511 512 // Also used for Thumb2 513 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 514 "blx${p}\t$func", 515 [(ARMcall GPR:$func)]>, 516 Requires<[IsThumb, HasV5T]>, 517 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 518 bits<4> func; 519 let Inst{6-3} = func; 520 let Inst{2-0} = 0b000; 521 } 522 523 // ARMv8-M Security Extensions 524 def tBLXNSr : TI<(outs), (ins pred:$p, GPRnopc:$func), IIC_Br, 525 "blxns${p}\t$func", []>, 526 Requires<[IsThumb, Has8MSecExt]>, 527 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { 528 bits<4> func; 529 let Inst{6-3} = func; 530 let Inst{2-0} = 0b100; 531 let Unpredictable{1-0} = 0b11; 532 } 533 534 // ARMv4T 535 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 536 4, IIC_Br, 537 [(ARMcall_nolink tGPR:$func)]>, 538 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 539 } 540 541 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 542 let isPredicable = 1 in 543 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 544 "b", "\t$target", [(br bb:$target)]>, 545 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 546 bits<11> target; 547 let Inst{10-0} = target; 548 let AsmMatchConverter = "cvtThumbBranches"; 549 } 550 551 // Far jump 552 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 553 // the clobber of LR. 554 let Defs = [LR] in 555 def tBfar : tPseudoExpand<(outs), (ins thumb_bl_target:$target, pred:$p), 556 4, IIC_Br, [], 557 (tBL pred:$p, thumb_bl_target:$target)>, 558 Sched<[WriteBrTbl]>; 559 560 def tBR_JTr : tPseudoInst<(outs), 561 (ins tGPR:$target, i32imm:$jt), 562 0, IIC_Br, 563 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>, 564 Sched<[WriteBrTbl]> { 565 let Size = 2; 566 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 567 } 568 } 569 570 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 571 // a two-value operand where a dag node expects two operands. :( 572 let isBranch = 1, isTerminator = 1 in 573 def tBcc : T1I<(outs), (ins thumb_bcc_target:$target, pred:$p), IIC_Br, 574 "b${p}\t$target", 575 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 576 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 577 bits<4> p; 578 bits<8> target; 579 let Inst{11-8} = p; 580 let Inst{7-0} = target; 581 let AsmMatchConverter = "cvtThumbBranches"; 582 } 583 584 585 // Tail calls 586 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 587 // IOS versions. 588 let Uses = [SP] in { 589 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 590 4, IIC_Br, [], 591 (tBX GPR:$dst, (ops 14, zero_reg))>, 592 Requires<[IsThumb]>, Sched<[WriteBr]>; 593 } 594 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls 595 // on MachO), so it's in ARMInstrThumb2.td. 596 // Non-MachO version: 597 let Uses = [SP] in { 598 def tTAILJMPdND : tPseudoExpand<(outs), 599 (ins t_brtarget:$dst, pred:$p), 600 4, IIC_Br, [], 601 (tB t_brtarget:$dst, pred:$p)>, 602 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>; 603 } 604 } 605 606 607 // A8.6.218 Supervisor Call (Software Interrupt) 608 // A8.6.16 B: Encoding T1 609 // If Inst{11-8} == 0b1111 then SEE SVC 610 let isCall = 1, Uses = [SP] in 611 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 612 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 613 bits<8> imm; 614 let Inst{15-12} = 0b1101; 615 let Inst{11-8} = 0b1111; 616 let Inst{7-0} = imm; 617 } 618 619 // The assembler uses 0xDEFE for a trap instruction. 620 let isBarrier = 1, isTerminator = 1 in 621 def tTRAP : TI<(outs), (ins), IIC_Br, 622 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 623 let Inst = 0xdefe; 624 } 625 626 //===----------------------------------------------------------------------===// 627 // Load Store Instructions. 628 // 629 630 // PC-relative loads need to be matched first as constant pool accesses need to 631 // always be PC-relative. We do this using AddedComplexity, as the pattern is 632 // simpler than the patterns of the other load instructions. 633 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in 634 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 635 "ldr", "\t$Rt, $addr", 636 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 637 T1Encoding<{0,1,0,0,1,?}> { 638 // A6.2 & A8.6.59 639 bits<3> Rt; 640 bits<8> addr; 641 let Inst{10-8} = Rt; 642 let Inst{7-0} = addr; 643 } 644 645 // SP-relative loads should be matched before standard immediate-offset loads as 646 // it means we avoid having to move SP to another register. 647 let canFoldAsLoad = 1 in 648 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 649 "ldr", "\t$Rt, $addr", 650 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 651 T1LdStSP<{1,?,?}> { 652 bits<3> Rt; 653 bits<8> addr; 654 let Inst{10-8} = Rt; 655 let Inst{7-0} = addr; 656 } 657 658 // Loads: reg/reg and reg/imm5 659 let canFoldAsLoad = 1, isReMaterializable = 1 in 660 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 661 Operand AddrMode_r, Operand AddrMode_i, 662 AddrMode am, InstrItinClass itin_r, 663 InstrItinClass itin_i, string asm, 664 PatFrag opnode> { 665 // Immediate-offset loads should be matched before register-offset loads as 666 // when the offset is a constant it's simpler to first check if it fits in the 667 // immediate offset field then fall back to register-offset if it doesn't. 668 def i : // reg/imm5 669 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 670 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 671 am, itin_i, asm, "\t$Rt, $addr", 672 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 673 // Register-offset loads are matched last. 674 def r : // reg/reg 675 T1pILdStEncode<reg_opc, 676 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 677 am, itin_r, asm, "\t$Rt, $addr", 678 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 679 } 680 // Stores: reg/reg and reg/imm5 681 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 682 Operand AddrMode_r, Operand AddrMode_i, 683 AddrMode am, InstrItinClass itin_r, 684 InstrItinClass itin_i, string asm, 685 PatFrag opnode> { 686 def i : // reg/imm5 687 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 688 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 689 am, itin_i, asm, "\t$Rt, $addr", 690 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 691 def r : // reg/reg 692 T1pILdStEncode<reg_opc, 693 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 694 am, itin_r, asm, "\t$Rt, $addr", 695 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 696 } 697 698 // A8.6.57 & A8.6.60 699 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr, 700 t_addrmode_is4, AddrModeT1_4, 701 IIC_iLoad_r, IIC_iLoad_i, "ldr", 702 load>; 703 704 // A8.6.64 & A8.6.61 705 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr, 706 t_addrmode_is1, AddrModeT1_1, 707 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 708 zextloadi8>; 709 710 // A8.6.76 & A8.6.73 711 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr, 712 t_addrmode_is2, AddrModeT1_2, 713 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 714 zextloadi16>; 715 716 let AddedComplexity = 10 in 717 def tLDRSB : // A8.6.80 718 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 719 AddrModeT1_1, IIC_iLoad_bh_r, 720 "ldrsb", "\t$Rt, $addr", 721 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 722 723 let AddedComplexity = 10 in 724 def tLDRSH : // A8.6.84 725 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 726 AddrModeT1_2, IIC_iLoad_bh_r, 727 "ldrsh", "\t$Rt, $addr", 728 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 729 730 731 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 732 "str", "\t$Rt, $addr", 733 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 734 T1LdStSP<{0,?,?}> { 735 bits<3> Rt; 736 bits<8> addr; 737 let Inst{10-8} = Rt; 738 let Inst{7-0} = addr; 739 } 740 741 // A8.6.194 & A8.6.192 742 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr, 743 t_addrmode_is4, AddrModeT1_4, 744 IIC_iStore_r, IIC_iStore_i, "str", 745 store>; 746 747 // A8.6.197 & A8.6.195 748 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr, 749 t_addrmode_is1, AddrModeT1_1, 750 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 751 truncstorei8>; 752 753 // A8.6.207 & A8.6.205 754 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr, 755 t_addrmode_is2, AddrModeT1_2, 756 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 757 truncstorei16>; 758 759 760 //===----------------------------------------------------------------------===// 761 // Load / store multiple Instructions. 762 // 763 764 // These require base address to be written back or one of the loaded regs. 765 let hasSideEffects = 0 in { 766 767 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 768 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 769 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 770 bits<3> Rn; 771 bits<8> regs; 772 let Inst{10-8} = Rn; 773 let Inst{7-0} = regs; 774 } 775 776 // Writeback version is just a pseudo, as there's no encoding difference. 777 // Writeback happens iff the base register is not in the destination register 778 // list. 779 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 780 def tLDMIA_UPD : 781 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 782 "$Rn = $wb", IIC_iLoad_mu>, 783 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 784 let Size = 2; 785 let OutOperandList = (outs GPR:$wb); 786 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 787 let Pattern = []; 788 let isCodeGenOnly = 1; 789 let isPseudo = 1; 790 list<Predicate> Predicates = [IsThumb]; 791 } 792 793 // There is no non-writeback version of STM for Thumb. 794 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 795 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 796 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 797 AddrModeNone, 2, IIC_iStore_mu, 798 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 799 T1Encoding<{1,1,0,0,0,?}> { 800 bits<3> Rn; 801 bits<8> regs; 802 let Inst{10-8} = Rn; 803 let Inst{7-0} = regs; 804 } 805 806 } // hasSideEffects 807 808 def : InstAlias<"ldm${p} $Rn!, $regs", 809 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>, 810 Requires<[IsThumb, IsThumb1Only]>; 811 812 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 813 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 814 IIC_iPop, 815 "pop${p}\t$regs", []>, 816 T1Misc<{1,1,0,?,?,?,?}> { 817 bits<16> regs; 818 let Inst{8} = regs{15}; 819 let Inst{7-0} = regs{7-0}; 820 } 821 822 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 823 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 824 IIC_iStore_m, 825 "push${p}\t$regs", []>, 826 T1Misc<{0,1,0,?,?,?,?}> { 827 bits<16> regs; 828 let Inst{8} = regs{14}; 829 let Inst{7-0} = regs{7-0}; 830 } 831 832 //===----------------------------------------------------------------------===// 833 // Arithmetic Instructions. 834 // 835 836 // Helper classes for encoding T1pI patterns: 837 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 838 string opc, string asm, list<dag> pattern> 839 : T1pI<oops, iops, itin, opc, asm, pattern>, 840 T1DataProcessing<opA> { 841 bits<3> Rm; 842 bits<3> Rn; 843 let Inst{5-3} = Rm; 844 let Inst{2-0} = Rn; 845 } 846 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 847 string opc, string asm, list<dag> pattern> 848 : T1pI<oops, iops, itin, opc, asm, pattern>, 849 T1Misc<opA> { 850 bits<3> Rm; 851 bits<3> Rd; 852 let Inst{5-3} = Rm; 853 let Inst{2-0} = Rd; 854 } 855 856 // Helper classes for encoding T1sI patterns: 857 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 858 string opc, string asm, list<dag> pattern> 859 : T1sI<oops, iops, itin, opc, asm, pattern>, 860 T1DataProcessing<opA> { 861 bits<3> Rd; 862 bits<3> Rn; 863 let Inst{5-3} = Rn; 864 let Inst{2-0} = Rd; 865 } 866 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 867 string opc, string asm, list<dag> pattern> 868 : T1sI<oops, iops, itin, opc, asm, pattern>, 869 T1General<opA> { 870 bits<3> Rm; 871 bits<3> Rn; 872 bits<3> Rd; 873 let Inst{8-6} = Rm; 874 let Inst{5-3} = Rn; 875 let Inst{2-0} = Rd; 876 } 877 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 878 string opc, string asm, list<dag> pattern> 879 : T1sI<oops, iops, itin, opc, asm, pattern>, 880 T1General<opA> { 881 bits<3> Rd; 882 bits<3> Rm; 883 let Inst{5-3} = Rm; 884 let Inst{2-0} = Rd; 885 } 886 887 // Helper classes for encoding T1sIt patterns: 888 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 889 string opc, string asm, list<dag> pattern> 890 : T1sIt<oops, iops, itin, opc, asm, pattern>, 891 T1DataProcessing<opA> { 892 bits<3> Rdn; 893 bits<3> Rm; 894 let Inst{5-3} = Rm; 895 let Inst{2-0} = Rdn; 896 } 897 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 898 string opc, string asm, list<dag> pattern> 899 : T1sIt<oops, iops, itin, opc, asm, pattern>, 900 T1General<opA> { 901 bits<3> Rdn; 902 bits<8> imm8; 903 let Inst{10-8} = Rdn; 904 let Inst{7-0} = imm8; 905 } 906 907 // Add with carry register 908 let isCommutable = 1, Uses = [CPSR] in 909 def tADC : // A8.6.2 910 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 911 "adc", "\t$Rdn, $Rm", 912 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 913 914 // Add immediate 915 def tADDi3 : // A8.6.4 T1 916 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 917 IIC_iALUi, 918 "add", "\t$Rd, $Rm, $imm3", 919 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 920 Sched<[WriteALU]> { 921 bits<3> imm3; 922 let Inst{8-6} = imm3; 923 } 924 925 def tADDi8 : // A8.6.4 T2 926 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 927 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 928 "add", "\t$Rdn, $imm8", 929 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 930 Sched<[WriteALU]>; 931 932 // Add register 933 let isCommutable = 1 in 934 def tADDrr : // A8.6.6 T1 935 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 936 IIC_iALUr, 937 "add", "\t$Rd, $Rn, $Rm", 938 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 939 940 let hasSideEffects = 0 in 941 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 942 "add", "\t$Rdn, $Rm", []>, 943 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 944 // A8.6.6 T2 945 bits<4> Rdn; 946 bits<4> Rm; 947 let Inst{7} = Rdn{3}; 948 let Inst{6-3} = Rm; 949 let Inst{2-0} = Rdn{2-0}; 950 } 951 952 // AND register 953 let isCommutable = 1 in 954 def tAND : // A8.6.12 955 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 956 IIC_iBITr, 957 "and", "\t$Rdn, $Rm", 958 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 959 960 // ASR immediate 961 def tASRri : // A8.6.14 962 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 963 IIC_iMOVsi, 964 "asr", "\t$Rd, $Rm, $imm5", 965 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 966 Sched<[WriteALU]> { 967 bits<5> imm5; 968 let Inst{10-6} = imm5; 969 } 970 971 // ASR register 972 def tASRrr : // A8.6.15 973 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 974 IIC_iMOVsr, 975 "asr", "\t$Rdn, $Rm", 976 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 977 978 // BIC register 979 def tBIC : // A8.6.20 980 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 981 IIC_iBITr, 982 "bic", "\t$Rdn, $Rm", 983 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 984 Sched<[WriteALU]>; 985 986 // CMN register 987 let isCompare = 1, Defs = [CPSR] in { 988 //FIXME: Disable CMN, as CCodes are backwards from compare expectations 989 // Compare-to-zero still works out, just not the relationals 990 //def tCMN : // A8.6.33 991 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 992 // IIC_iCMPr, 993 // "cmn", "\t$lhs, $rhs", 994 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 995 996 def tCMNz : // A8.6.33 997 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 998 IIC_iCMPr, 999 "cmn", "\t$Rn, $Rm", 1000 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 1001 1002 } // isCompare = 1, Defs = [CPSR] 1003 1004 // CMP immediate 1005 let isCompare = 1, Defs = [CPSR] in { 1006 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 1007 "cmp", "\t$Rn, $imm8", 1008 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 1009 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 1010 // A8.6.35 1011 bits<3> Rn; 1012 bits<8> imm8; 1013 let Inst{10-8} = Rn; 1014 let Inst{7-0} = imm8; 1015 } 1016 1017 // CMP register 1018 def tCMPr : // A8.6.36 T1 1019 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1020 IIC_iCMPr, 1021 "cmp", "\t$Rn, $Rm", 1022 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 1023 1024 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 1025 "cmp", "\t$Rn, $Rm", []>, 1026 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 1027 // A8.6.36 T2 1028 bits<4> Rm; 1029 bits<4> Rn; 1030 let Inst{7} = Rn{3}; 1031 let Inst{6-3} = Rm; 1032 let Inst{2-0} = Rn{2-0}; 1033 } 1034 } // isCompare = 1, Defs = [CPSR] 1035 1036 1037 // XOR register 1038 let isCommutable = 1 in 1039 def tEOR : // A8.6.45 1040 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1041 IIC_iBITr, 1042 "eor", "\t$Rdn, $Rm", 1043 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1044 1045 // LSL immediate 1046 def tLSLri : // A8.6.88 1047 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 1048 IIC_iMOVsi, 1049 "lsl", "\t$Rd, $Rm, $imm5", 1050 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 1051 Sched<[WriteALU]> { 1052 bits<5> imm5; 1053 let Inst{10-6} = imm5; 1054 } 1055 1056 // LSL register 1057 def tLSLrr : // A8.6.89 1058 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1059 IIC_iMOVsr, 1060 "lsl", "\t$Rdn, $Rm", 1061 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1062 1063 // LSR immediate 1064 def tLSRri : // A8.6.90 1065 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1066 IIC_iMOVsi, 1067 "lsr", "\t$Rd, $Rm, $imm5", 1068 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1069 Sched<[WriteALU]> { 1070 bits<5> imm5; 1071 let Inst{10-6} = imm5; 1072 } 1073 1074 // LSR register 1075 def tLSRrr : // A8.6.91 1076 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1077 IIC_iMOVsr, 1078 "lsr", "\t$Rdn, $Rm", 1079 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1080 1081 // Move register 1082 let isMoveImm = 1 in 1083 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1084 "mov", "\t$Rd, $imm8", 1085 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1086 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1087 // A8.6.96 1088 bits<3> Rd; 1089 bits<8> imm8; 1090 let Inst{10-8} = Rd; 1091 let Inst{7-0} = imm8; 1092 } 1093 // Because we have an explicit tMOVSr below, we need an alias to handle 1094 // the immediate "movs" form here. Blech. 1095 def : tInstAlias <"movs $Rdn, $imm", 1096 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1097 1098 // A7-73: MOV(2) - mov setting flag. 1099 1100 let hasSideEffects = 0 in { 1101 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1102 2, IIC_iMOVr, 1103 "mov", "\t$Rd, $Rm", "", []>, 1104 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1105 // A8.6.97 1106 bits<4> Rd; 1107 bits<4> Rm; 1108 let Inst{7} = Rd{3}; 1109 let Inst{6-3} = Rm; 1110 let Inst{2-0} = Rd{2-0}; 1111 } 1112 let Defs = [CPSR] in 1113 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1114 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1115 // A8.6.97 1116 bits<3> Rd; 1117 bits<3> Rm; 1118 let Inst{15-6} = 0b0000000000; 1119 let Inst{5-3} = Rm; 1120 let Inst{2-0} = Rd; 1121 } 1122 } // hasSideEffects 1123 1124 // Multiply register 1125 let isCommutable = 1 in 1126 def tMUL : // A8.6.105 T1 1127 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1128 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1129 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1130 T1DataProcessing<0b1101> { 1131 bits<3> Rd; 1132 bits<3> Rn; 1133 let Inst{5-3} = Rn; 1134 let Inst{2-0} = Rd; 1135 let AsmMatchConverter = "cvtThumbMultiply"; 1136 } 1137 1138 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1139 pred:$p)>; 1140 1141 // Move inverse register 1142 def tMVN : // A8.6.107 1143 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1144 "mvn", "\t$Rd, $Rn", 1145 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1146 1147 // Bitwise or register 1148 let isCommutable = 1 in 1149 def tORR : // A8.6.114 1150 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1151 IIC_iBITr, 1152 "orr", "\t$Rdn, $Rm", 1153 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1154 1155 // Swaps 1156 def tREV : // A8.6.134 1157 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1158 IIC_iUNAr, 1159 "rev", "\t$Rd, $Rm", 1160 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1161 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1162 1163 def tREV16 : // A8.6.135 1164 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1165 IIC_iUNAr, 1166 "rev16", "\t$Rd, $Rm", 1167 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1168 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1169 1170 def tREVSH : // A8.6.136 1171 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1172 IIC_iUNAr, 1173 "revsh", "\t$Rd, $Rm", 1174 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1175 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1176 1177 // Rotate right register 1178 def tROR : // A8.6.139 1179 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1180 IIC_iMOVsr, 1181 "ror", "\t$Rdn, $Rm", 1182 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1183 Sched<[WriteALU]>; 1184 1185 // Negate register 1186 def tRSB : // A8.6.141 1187 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1188 IIC_iALUi, 1189 "rsb", "\t$Rd, $Rn, #0", 1190 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1191 1192 // Subtract with carry register 1193 let Uses = [CPSR] in 1194 def tSBC : // A8.6.151 1195 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1196 IIC_iALUr, 1197 "sbc", "\t$Rdn, $Rm", 1198 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1199 Sched<[WriteALU]>; 1200 1201 // Subtract immediate 1202 def tSUBi3 : // A8.6.210 T1 1203 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1204 IIC_iALUi, 1205 "sub", "\t$Rd, $Rm, $imm3", 1206 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1207 Sched<[WriteALU]> { 1208 bits<3> imm3; 1209 let Inst{8-6} = imm3; 1210 } 1211 1212 def tSUBi8 : // A8.6.210 T2 1213 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1214 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1215 "sub", "\t$Rdn, $imm8", 1216 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1217 Sched<[WriteALU]>; 1218 1219 // Subtract register 1220 def tSUBrr : // A8.6.212 1221 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1222 IIC_iALUr, 1223 "sub", "\t$Rd, $Rn, $Rm", 1224 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1225 Sched<[WriteALU]>; 1226 1227 // Sign-extend byte 1228 def tSXTB : // A8.6.222 1229 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1230 IIC_iUNAr, 1231 "sxtb", "\t$Rd, $Rm", 1232 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1233 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1234 Sched<[WriteALU]>; 1235 1236 // Sign-extend short 1237 def tSXTH : // A8.6.224 1238 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1239 IIC_iUNAr, 1240 "sxth", "\t$Rd, $Rm", 1241 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1242 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1243 Sched<[WriteALU]>; 1244 1245 // Test 1246 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1247 def tTST : // A8.6.230 1248 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1249 "tst", "\t$Rn, $Rm", 1250 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1251 Sched<[WriteALU]>; 1252 1253 // A8.8.247 UDF - Undefined (Encoding T1) 1254 def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", 1255 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 { 1256 bits<8> imm8; 1257 let Inst{15-12} = 0b1101; 1258 let Inst{11-8} = 0b1110; 1259 let Inst{7-0} = imm8; 1260 } 1261 1262 // Zero-extend byte 1263 def tUXTB : // A8.6.262 1264 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1265 IIC_iUNAr, 1266 "uxtb", "\t$Rd, $Rm", 1267 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1268 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1269 Sched<[WriteALU]>; 1270 1271 // Zero-extend short 1272 def tUXTH : // A8.6.264 1273 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1274 IIC_iUNAr, 1275 "uxth", "\t$Rd, $Rm", 1276 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1277 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1278 1279 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1280 // Expanded after instruction selection into a branch sequence. 1281 let usesCustomInserter = 1 in // Expanded after instruction selection. 1282 def tMOVCCr_pseudo : 1283 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), 1284 NoItinerary, 1285 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; 1286 1287 // tLEApcrel - Load a pc-relative address into a register without offending the 1288 // assembler. 1289 1290 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1291 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1292 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1293 bits<3> Rd; 1294 bits<8> addr; 1295 let Inst{10-8} = Rd; 1296 let Inst{7-0} = addr; 1297 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1298 } 1299 1300 let hasSideEffects = 0, isReMaterializable = 1 in 1301 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1302 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1303 1304 let hasSideEffects = 1 in 1305 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1306 (ins i32imm:$label, pred:$p), 1307 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1308 1309 //===----------------------------------------------------------------------===// 1310 // TLS Instructions 1311 // 1312 1313 // __aeabi_read_tp preserves the registers r1-r3. 1314 // This is a pseudo inst so that we can get the encoding right, 1315 // complete with fixup for the aeabi_read_tp function. 1316 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1317 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1318 [(set R0, ARMthread_pointer)]>, 1319 Sched<[WriteBr]>; 1320 1321 //===----------------------------------------------------------------------===// 1322 // SJLJ Exception handling intrinsics 1323 // 1324 1325 // eh_sjlj_setjmp() is an instruction sequence to store the return address and 1326 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1327 // from some other function to get here, and we're using the stack frame for the 1328 // containing function to save/restore registers, we can't keep anything live in 1329 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1330 // tromped upon when we get here from a longjmp(). We force everything out of 1331 // registers except for our own input by listing the relevant registers in 1332 // Defs. By doing so, we also cause the prologue/epilogue code to actively 1333 // preserve all of the callee-saved resgisters, which is exactly what we want. 1334 // $val is a scratch register for our use. 1335 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1336 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1337 usesCustomInserter = 1 in 1338 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1339 AddrModeNone, 0, NoItinerary, "","", 1340 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1341 1342 // FIXME: Non-IOS version(s) 1343 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1344 Defs = [ R7, LR, SP ] in 1345 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1346 AddrModeNone, 0, IndexModeNone, 1347 Pseudo, NoItinerary, "", "", 1348 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1349 Requires<[IsThumb,IsNotWindows]>; 1350 1351 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1352 Defs = [ R11, LR, SP ] in 1353 def tInt_WIN_eh_sjlj_longjmp 1354 : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone, 1355 Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1356 Requires<[IsThumb,IsWindows]>; 1357 1358 //===----------------------------------------------------------------------===// 1359 // Non-Instruction Patterns 1360 // 1361 1362 // Comparisons 1363 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1364 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1365 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1366 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1367 1368 // Add with carry 1369 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1370 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1371 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1372 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1373 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1374 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1375 1376 // Subtract with carry 1377 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1378 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1379 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1380 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1381 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1382 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1383 1384 // Bswap 16 with load/store 1385 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)), 1386 (tREV16 (tLDRHi t_addrmode_is2:$addr))>; 1387 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)), 1388 (tREV16 (tLDRHr t_addrmode_rr:$addr))>; 1389 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1390 t_addrmode_is2:$addr), 1391 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>; 1392 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)), 1393 t_addrmode_rr:$addr), 1394 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>; 1395 1396 // ConstantPool 1397 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1398 1399 // GlobalAddress 1400 def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr), 1401 IIC_iLoadiALU, 1402 [(set tGPR:$dst, 1403 (ARMWrapperPIC tglobaladdr:$addr))]>, 1404 Requires<[IsThumb, DontUseMovt]>; 1405 1406 def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src), 1407 IIC_iLoad_i, 1408 [(set tGPR:$dst, 1409 (ARMWrapper tglobaladdr:$src))]>, 1410 Requires<[IsThumb, DontUseMovt]>; 1411 1412 // TLS globals 1413 def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 1414 (tLDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 1415 Requires<[IsThumb, DontUseMovt]>; 1416 def : Pat<(ARMWrapper tglobaltlsaddr:$addr), 1417 (tLDRLIT_ga_abs tglobaltlsaddr:$addr)>, 1418 Requires<[IsThumb, DontUseMovt]>; 1419 1420 1421 // JumpTable 1422 def : T1Pat<(ARMWrapperJT tjumptable:$dst), 1423 (tLEApcrelJT tjumptable:$dst)>; 1424 1425 // Direct calls 1426 def : T1Pat<(ARMcall texternalsym:$func), (tBL texternalsym:$func)>, 1427 Requires<[IsThumb]>; 1428 1429 // zextload i1 -> zextload i8 1430 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1431 (tLDRBi t_addrmode_is1:$addr)>; 1432 def : T1Pat<(zextloadi1 t_addrmode_rr:$addr), 1433 (tLDRBr t_addrmode_rr:$addr)>; 1434 1435 // extload from the stack -> word load from the stack, as it avoids having to 1436 // materialize the base in a separate register. This only works when a word 1437 // load puts the byte/halfword value in the same place in the register that the 1438 // byte/halfword load would, i.e. when little-endian. 1439 def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1440 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1441 def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1442 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1443 def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>, 1444 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1445 1446 // extload -> zextload 1447 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1448 def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1449 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1450 def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>; 1451 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1452 def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>; 1453 1454 // If it's impossible to use [r,r] address mode for sextload, select to 1455 // ldr{b|h} + sxt{b|h} instead. 1456 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1457 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1458 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1459 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1460 (tSXTB (tLDRBr t_addrmode_rr:$addr))>, 1461 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1462 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1463 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1464 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1465 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1466 (tSXTH (tLDRHr t_addrmode_rr:$addr))>, 1467 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1468 1469 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1470 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1471 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr), 1472 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>; 1473 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1474 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1475 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr), 1476 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>; 1477 1478 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1479 (tLDRBi t_addrmode_is1:$src)>; 1480 def : T1Pat<(atomic_load_8 t_addrmode_rr:$src), 1481 (tLDRBr t_addrmode_rr:$src)>; 1482 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1483 (tLDRHi t_addrmode_is2:$src)>; 1484 def : T1Pat<(atomic_load_16 t_addrmode_rr:$src), 1485 (tLDRHr t_addrmode_rr:$src)>; 1486 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1487 (tLDRi t_addrmode_is4:$src)>; 1488 def : T1Pat<(atomic_load_32 t_addrmode_rr:$src), 1489 (tLDRr t_addrmode_rr:$src)>; 1490 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1491 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1492 def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val), 1493 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>; 1494 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1495 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1496 def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val), 1497 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>; 1498 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1499 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1500 def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val), 1501 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>; 1502 1503 // Large immediate handling. 1504 1505 // Two piece imms. 1506 def : T1Pat<(i32 thumb_immshifted:$src), 1507 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1508 (thumb_immshifted_shamt imm:$src))>; 1509 1510 def : T1Pat<(i32 imm0_255_comp:$src), 1511 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1512 1513 def : T1Pat<(i32 imm256_510:$src), 1514 (tADDi8 (tMOVi8 255), 1515 (thumb_imm256_510_addend imm:$src))>; 1516 1517 // Pseudo instruction that combines ldr from constpool and add pc. This should 1518 // be expanded into two instructions late to allow if-conversion and 1519 // scheduling. 1520 let isReMaterializable = 1 in 1521 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1522 NoItinerary, 1523 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1524 imm:$cp))]>, 1525 Requires<[IsThumb, IsThumb1Only]>; 1526 1527 // Pseudo-instruction for merged POP and return. 1528 // FIXME: remove when we have a way to marking a MI with these properties. 1529 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1530 hasExtraDefRegAllocReq = 1 in 1531 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1532 2, IIC_iPop_Br, [], 1533 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1534 1535 // Indirect branch using "mov pc, $Rm" 1536 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1537 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1538 2, IIC_Br, [(brind GPR:$Rm)], 1539 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1540 } 1541 1542 1543 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1544 // encoding is available on ARMv6K, but we don't differentiate that finely. 1545 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0), 0>, Requires<[IsThumb, IsThumb1Only]>; 1546 1547 1548 // For round-trip assembly/disassembly, we have to handle a CPS instruction 1549 // without any iflags. That's not, strictly speaking, valid syntax, but it's 1550 // a useful extension and assembles to defined behaviour (the insn does 1551 // nothing). 1552 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1553 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1554 1555 // "neg" is and alias for "rsb rd, rn, #0" 1556 def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1557 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1558 1559 1560 // Implied destination operand forms for shifts. 1561 def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1562 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1563 def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1564 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1565 def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1566 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1567 1568 // Pseudo instruction ldr Rt, =immediate 1569 def tLDRConstPool 1570 : tAsmPseudo<"ldr${p} $Rt, $immediate", 1571 (ins tGPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>; 1572
