1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Hexagon V3 instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall, 15 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 16 17 def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall, 18 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 19 20 //===----------------------------------------------------------------------===// 21 // J + 22 //===----------------------------------------------------------------------===// 23 // Call subroutine. 24 let isCall = 1, hasSideEffects = 1, isPredicable = 1, 25 isExtended = 0, isExtendable = 1, opExtendable = 0, 26 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in 27 class T_Call<bit CSR, string ExtStr> 28 : JInst<(outs), (ins calltarget:$dst), 29 "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> { 30 let BaseOpcode = "call"; 31 bits<24> dst; 32 33 let Defs = !if (CSR, VolatileV3.Regs, []); 34 let IClass = 0b0101; 35 let Inst{27-25} = 0b101; 36 let Inst{24-16,13-1} = dst{23-2}; 37 let Inst{0} = 0b0; 38 } 39 40 let isCall = 1, hasSideEffects = 1, isPredicated = 1, 41 isExtended = 0, isExtendable = 1, opExtendable = 1, 42 isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in 43 class T_CallPred<bit CSR, bit IfTrue, string ExtStr> 44 : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst), 45 CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst", 46 [], "", J_tc_2early_SLOT23> { 47 let BaseOpcode = "call"; 48 let isPredicatedFalse = !if(IfTrue,0,1); 49 bits<2> Pu; 50 bits<17> dst; 51 52 let Defs = !if (CSR, VolatileV3.Regs, []); 53 let IClass = 0b0101; 54 let Inst{27-24} = 0b1101; 55 let Inst{23-22,20-16,13,7-1} = dst{16-2}; 56 let Inst{21} = !if(IfTrue,0,1); 57 let Inst{11} = 0b0; 58 let Inst{9-8} = Pu; 59 } 60 61 multiclass T_Calls<bit CSR, string ExtStr> { 62 def NAME : T_Call<CSR, ExtStr>; 63 def t : T_CallPred<CSR, 1, ExtStr>; 64 def f : T_CallPred<CSR, 0, ExtStr>; 65 } 66 67 defm J2_call: T_Calls<1, "">, PredRel; 68 69 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in 70 def CALLv3nr : T_Call<1, "">, PredRel; 71 72 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [PC, R31, R6, R7, P0] in 73 def CALLstk : T_Call<0, "">, PredRel; 74 75 //===----------------------------------------------------------------------===// 76 // J - 77 //===----------------------------------------------------------------------===// 78 79 80 //===----------------------------------------------------------------------===// 81 // JR + 82 //===----------------------------------------------------------------------===// 83 // Call subroutine from register. 84 85 let isCodeGenOnly = 1, Defs = VolatileV3.Regs in { 86 def CALLRv3nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return. 87 } 88 89 //===----------------------------------------------------------------------===// 90 // JR - 91 //===----------------------------------------------------------------------===// 92 93 //===----------------------------------------------------------------------===// 94 // ALU64/ALU + 95 //===----------------------------------------------------------------------===// 96 97 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in 98 def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>; 99 100 class T_ALU64_addsp_hl<string suffix, bits<3> MinOp> 101 : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">; 102 103 def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>; 104 def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>; 105 106 let hasSideEffects = 0, isAsmParserOnly = 1 in 107 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd), 108 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)", 109 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))), 110 (i64 DoubleRegs:$Rt))))], 111 "", ALU64_tc_1_SLOT23>; 112 113 114 let hasSideEffects = 0 in 115 class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned> 116 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs), 117 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","") 118 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> { 119 bits<5> Rd; 120 bits<5> Rs; 121 bits<5> Rt; 122 123 let IClass = 0b1101; 124 125 let Inst{27-23} = 0b00111; 126 let Inst{22-21} = !if(isMax, 0b10, 0b01); 127 let Inst{20-16} = !if(isMax, Rt, Rs); 128 let Inst{12-8} = !if(isMax, Rs, Rt); 129 let Inst{7} = 0b1; 130 let Inst{6} = !if(isMax, 0b0, 0b1); 131 let Inst{5} = isUnsigned; 132 let Inst{4-0} = Rd; 133 } 134 135 def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>; 136 def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>; 137 def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>; 138 def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>; 139 140 multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> { 141 defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>; 142 } 143 144 let AddedComplexity = 200 in { 145 defm: MinMax_pats_p<setge, A2_maxp, A2_minp>; 146 defm: MinMax_pats_p<setgt, A2_maxp, A2_minp>; 147 defm: MinMax_pats_p<setle, A2_minp, A2_maxp>; 148 defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>; 149 defm: MinMax_pats_p<setuge, A2_maxup, A2_minup>; 150 defm: MinMax_pats_p<setugt, A2_maxup, A2_minup>; 151 defm: MinMax_pats_p<setule, A2_minup, A2_maxup>; 152 defm: MinMax_pats_p<setult, A2_minup, A2_maxup>; 153 } 154 155 //===----------------------------------------------------------------------===// 156 // ALU64/ALU - 157 //===----------------------------------------------------------------------===// 158 159 160 161 162 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset), 163 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>; 164 165 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset), 166 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>; 167 168 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset), 169 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>; 170 171 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset), 172 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>; 173 174 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset), 175 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>; 176 177 // Map call instruction 178 def : Pat<(callv3 (i32 IntRegs:$dst)), 179 (J2_callr (i32 IntRegs:$dst))>; 180 def : Pat<(callv3 tglobaladdr:$dst), 181 (J2_call tglobaladdr:$dst)>; 182 def : Pat<(callv3 texternalsym:$dst), 183 (J2_call texternalsym:$dst)>; 184 def : Pat<(callv3 tglobaltlsaddr:$dst), 185 (J2_call tglobaltlsaddr:$dst)>; 186 187 def : Pat<(callv3nr (i32 IntRegs:$dst)), 188 (CALLRv3nr (i32 IntRegs:$dst))>; 189 def : Pat<(callv3nr tglobaladdr:$dst), 190 (CALLv3nr tglobaladdr:$dst)>; 191 def : Pat<(callv3nr texternalsym:$dst), 192 (CALLv3nr texternalsym:$dst)>; 193 194 //===----------------------------------------------------------------------===// 195 // :raw form of vrcmpys:hi/lo insns 196 //===----------------------------------------------------------------------===// 197 // Vector reduce complex multiply by scalar. 198 let Defs = [USR_OVF], hasSideEffects = 0 in 199 class T_vrcmpRaw<string HiLo, bits<3>MajOp>: 200 MInst<(outs DoubleRegs:$Rdd), 201 (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), 202 "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> { 203 bits<5> Rdd; 204 bits<5> Rss; 205 bits<5> Rtt; 206 207 let IClass = 0b1110; 208 209 let Inst{27-24} = 0b1000; 210 let Inst{23-21} = MajOp; 211 let Inst{20-16} = Rss; 212 let Inst{12-8} = Rtt; 213 let Inst{7-5} = 0b100; 214 let Inst{4-0} = Rdd; 215 } 216 217 def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>; 218 def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>; 219 220 // Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l 221 let hasSideEffects = 0, isAsmParserOnly = 1 in 222 def M2_vrcmpys_s1 223 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt), 224 "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">; 225 226 // Vector reduce complex multiply by scalar with accumulation. 227 let Defs = [USR_OVF], hasSideEffects = 0 in 228 class T_vrcmpys_acc<string HiLo, bits<3>MajOp>: 229 MInst <(outs DoubleRegs:$Rxx), 230 (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt), 231 "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [], 232 "$Rxx = $_src_"> { 233 bits<5> Rxx; 234 bits<5> Rss; 235 bits<5> Rtt; 236 237 let IClass = 0b1110; 238 239 let Inst{27-24} = 0b1010; 240 let Inst{23-21} = MajOp; 241 let Inst{20-16} = Rss; 242 let Inst{12-8} = Rtt; 243 let Inst{7-5} = 0b100; 244 let Inst{4-0} = Rxx; 245 } 246 247 def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>; 248 def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>; 249 250 // Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l 251 252 let isAsmParserOnly = 1 in 253 def M2_vrcmpys_acc_s1 254 : MInst <(outs DoubleRegs:$dst), 255 (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2), 256 "$dst += vrcmpys($src1, $src2):<<1:sat", [], 257 "$dst2 = $dst">; 258 259 def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>; 260 def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>; 261 262 // Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l 263 let isAsmParserOnly = 1 in 264 def M2_vrcmpys_s1rp 265 : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt), 266 "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">; 267 268 269 // S2_cabacdecbin: Cabac decode bin. 270 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in 271 def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>; 272
