1 //=- HexagonIntrinsicsV60.td - Target Description for Hexagon -*- tablegen *-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Hexagon V60 Compiler Intrinsics in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 15 let isCodeGenOnly = 1 in { 16 def HEXAGON_V6_vd0_pseudo : CVI_VA_Resource<(outs VectorRegs:$dst), 17 (ins ), 18 "$dst=#0", 19 [(set VectorRegs:$dst, (int_hexagon_V6_vd0 ))]>; 20 21 def HEXAGON_V6_vd0_pseudo_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst), 22 (ins ), 23 "$dst=#0", 24 [(set VectorRegs128B:$dst, (int_hexagon_V6_vd0_128B ))]>; 25 } 26 27 let isPseudo = 1 in 28 def HEXAGON_V6_vassignp : CVI_VA_Resource<(outs VecDblRegs:$dst), 29 (ins VecDblRegs:$src1), 30 "$dst=vassignp_W($src1)", 31 [(set VecDblRegs:$dst, (int_hexagon_V6_vassignp VecDblRegs:$src1))]>; 32 33 let isPseudo = 1 in 34 def HEXAGON_V6_vassignp_128B : CVI_VA_Resource<(outs VecDblRegs128B:$dst), 35 (ins VecDblRegs128B:$src1), 36 "$dst=vassignp_W_128B($src1)", 37 [(set VecDblRegs128B:$dst, (int_hexagon_V6_vassignp_128B 38 VecDblRegs128B:$src1))]>; 39 40 let isPseudo = 1 in 41 def HEXAGON_V6_lo : CVI_VA_Resource<(outs VectorRegs:$dst), 42 (ins VecDblRegs:$src1), 43 "$dst=lo_W($src1)", 44 [(set VectorRegs:$dst, (int_hexagon_V6_lo VecDblRegs:$src1))]>; 45 46 let isPseudo = 1 in 47 def HEXAGON_V6_hi : CVI_VA_Resource<(outs VectorRegs:$dst), 48 (ins VecDblRegs:$src1), 49 "$dst=hi_W($src1)", 50 [(set VectorRegs:$dst, (int_hexagon_V6_hi VecDblRegs:$src1))]>; 51 52 let isPseudo = 1 in 53 def HEXAGON_V6_lo_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst), 54 (ins VecDblRegs128B:$src1), 55 "$dst=lo_W($src1)", 56 [(set VectorRegs128B:$dst, (int_hexagon_V6_lo_128B VecDblRegs128B:$src1))]>; 57 58 let isPseudo = 1 in 59 def HEXAGON_V6_hi_128B : CVI_VA_Resource<(outs VectorRegs128B:$dst), 60 (ins VecDblRegs128B:$src1), 61 "$dst=hi_W($src1)", 62 [(set VectorRegs128B:$dst, (int_hexagon_V6_hi_128B VecDblRegs128B:$src1))]>; 63 64 let AddedComplexity = 100 in { 65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))), 66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >, 67 Requires<[UseHVXSgl]>; 68 69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))), 70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >, 71 Requires<[UseHVXSgl]>; 72 73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))), 74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), 75 subreg_loreg)) >, 76 Requires<[UseHVXDbl]>; 77 78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))), 79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), 80 subreg_hireg)) >, 81 Requires<[UseHVXDbl]>; 82 } 83 84 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))), 85 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1), 86 (A2_tfrsi 0x01010101)))>, 87 Requires<[UseHVXSgl]>; 88 89 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))), 90 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1), 91 (A2_tfrsi 0x01010101)))>, 92 Requires<[UseHVXSgl]>; 93 94 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))), 95 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1), 96 (A2_tfrsi 0x01010101)))>, 97 Requires<[UseHVXSgl]>; 98 99 def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))), 100 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1), 101 (A2_tfrsi 0x01010101)))>, 102 Requires<[UseHVXSgl]>; 103 104 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))), 105 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1), 106 (A2_tfrsi 0x01010101)))>, 107 Requires<[UseHVXSgl]>; 108 109 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))), 110 (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1), 111 (A2_tfrsi 0x01010101)))>, 112 Requires<[UseHVXSgl]>; 113 114 def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))), 115 (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1), 116 (A2_tfrsi 0x01010101)))>, 117 Requires<[UseHVXSgl]>; 118 119 def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))), 120 (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1), 121 (A2_tfrsi 0x01010101)))>, 122 Requires<[UseHVXSgl]>; 123 124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))), 125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1), 126 (A2_tfrsi 0x01010101)))>, 127 Requires<[UseHVXDbl]>; 128 129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))), 130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1), 131 (A2_tfrsi 0x01010101)))>, 132 Requires<[UseHVXDbl]>; 133 134 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))), 135 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1), 136 (A2_tfrsi 0x01010101)))>, 137 Requires<[UseHVXDbl]>; 138 139 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))), 140 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1), 141 (A2_tfrsi 0x01010101)))>, 142 Requires<[UseHVXDbl]>; 143 144 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 145 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 146 (A2_tfrsi 0x01010101)))>, 147 Requires<[UseHVXDbl]>; 148 149 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 150 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 151 (A2_tfrsi 0x01010101)))>, 152 Requires<[UseHVXDbl]>; 153 154 def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 155 (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 156 (A2_tfrsi 0x01010101)))>, 157 Requires<[UseHVXDbl]>; 158 159 def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 160 (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 161 (A2_tfrsi 0x01010101)))>, 162 Requires<[UseHVXDbl]>; 163 164 let AddedComplexity = 140 in { 165 def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)), 166 (V6_vS32b_ai IntRegs:$addr, 0, 167 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1), 168 (A2_tfrsi 0x01010101))))>, 169 Requires<[UseHVXSgl]>; 170 171 def : Pat <(v512i1 (load (i32 IntRegs:$addr))), 172 (v512i1 (V6_vandvrt 173 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>, 174 Requires<[UseHVXSgl]>; 175 176 def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)), 177 (V6_vS32b_ai_128B IntRegs:$addr, 0, 178 (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1), 179 (A2_tfrsi 0x01010101))))>, 180 Requires<[UseHVXDbl]>; 181 182 def : Pat <(v1024i1 (load (i32 IntRegs:$addr))), 183 (v1024i1 (V6_vandvrt_128B 184 (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)), 185 (A2_tfrsi 0x01010101)))>, 186 Requires<[UseHVXDbl]>; 187 } 188 189 multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> { 190 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>, 191 Requires<[UseHVXSgl]>; 192 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1), 193 (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>, 194 Requires<[UseHVXDbl]>; 195 } 196 197 multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> { 198 def: Pat<(IntID VectorRegs:$src1), 199 (MI VectorRegs:$src1)>, 200 Requires<[UseHVXSgl]>; 201 202 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1), 203 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1)>, 204 Requires<[UseHVXDbl]>; 205 } 206 207 multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> { 208 def: Pat<(IntID VecPredRegs:$src1), 209 (MI VecPredRegs:$src1)>, 210 Requires<[UseHVXSgl]>; 211 212 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1), 213 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1)>, 214 Requires<[UseHVXDbl]>; 215 } 216 217 multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> { 218 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2), 219 (MI VecDblRegs:$src1, IntRegs:$src2)>, 220 Requires<[UseHVXSgl]>; 221 222 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2), 223 (!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>, 224 Requires<[UseHVXDbl]>; 225 } 226 227 multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> { 228 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2), 229 (MI VectorRegs:$src1, IntRegs:$src2)>, 230 Requires<[UseHVXSgl]>; 231 232 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2), 233 (!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>, 234 Requires<[UseHVXDbl]>; 235 } 236 237 multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> { 238 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2), 239 (MI VecDblRegs:$src1, VectorRegs:$src2)>, 240 Requires<[UseHVXSgl]>; 241 242 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 243 VectorRegs128B:$src2), 244 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 245 VectorRegs128B:$src2)>, 246 Requires<[UseHVXDbl]>; 247 } 248 249 multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> { 250 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2), 251 (MI VecDblRegs:$src1, VecDblRegs:$src2)>, 252 Requires<[UseHVXSgl]>; 253 254 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 255 VecDblRegs128B:$src2), 256 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 257 VecDblRegs128B:$src2)>, 258 Requires<[UseHVXDbl]>; 259 } 260 261 multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> { 262 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2), 263 (MI VectorRegs:$src1, VectorRegs:$src2)>, 264 Requires<[UseHVXSgl]>; 265 266 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 267 VectorRegs128B:$src2), 268 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 269 VectorRegs128B:$src2)>, 270 Requires<[UseHVXDbl]>; 271 } 272 273 multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> { 274 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2), 275 (MI VecPredRegs:$src1, IntRegs:$src2)>, 276 Requires<[UseHVXSgl]>; 277 278 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, 279 IntRegs:$src2), 280 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, 281 IntRegs:$src2)>, 282 Requires<[UseHVXDbl]>; 283 } 284 285 multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> { 286 def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2), 287 (MI VecPredRegs:$src1, VecPredRegs:$src2)>, 288 Requires<[UseHVXSgl]>; 289 290 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, 291 VecPredRegs128B:$src2), 292 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, 293 VecPredRegs128B:$src2)>, 294 Requires<[UseHVXDbl]>; 295 } 296 297 multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> { 298 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), 299 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, 300 Requires<[UseHVXSgl]>; 301 302 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 303 VecDblRegs128B:$src2, 304 IntRegs:$src3), 305 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 306 VecDblRegs128B:$src2, 307 IntRegs:$src3)>, 308 Requires<[UseHVXDbl]>; 309 } 310 311 multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> { 312 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3), 313 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, 314 Requires<[UseHVXSgl]>; 315 316 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 317 VectorRegs128B:$src2, 318 IntRegs:$src3), 319 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 320 VectorRegs128B:$src2, 321 IntRegs:$src3)>, 322 Requires<[UseHVXDbl]>; 323 } 324 325 multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> { 326 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3), 327 (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, 328 Requires<[UseHVXSgl]>; 329 330 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 331 VectorRegs128B:$src2, 332 IntRegs:$src3), 333 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 334 VectorRegs128B:$src2, 335 IntRegs:$src3)>, 336 Requires<[UseHVXDbl]>; 337 } 338 339 multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> { 340 def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), 341 (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, 342 Requires<[UseHVXSgl]>; 343 344 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 345 VecDblRegs128B:$src2, 346 IntRegs:$src3), 347 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 348 VecDblRegs128B:$src2, 349 IntRegs:$src3)>, 350 Requires<[UseHVXDbl]>; 351 } 352 353 multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> { 354 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), 355 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, 356 Requires<[UseHVXSgl]>; 357 358 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 359 VectorRegs128B:$src2, 360 VectorRegs128B:$src3), 361 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 362 VectorRegs128B:$src2, 363 VectorRegs128B:$src3)>, 364 Requires<[UseHVXDbl]>; 365 } 366 367 multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> { 368 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), 369 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, 370 Requires<[UseHVXSgl]>; 371 372 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 373 VectorRegs128B:$src2, 374 VectorRegs128B:$src3), 375 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 376 VectorRegs128B:$src2, 377 VectorRegs128B:$src3)>, 378 Requires<[UseHVXDbl]>; 379 } 380 381 multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> { 382 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), 383 (MI VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, 384 Requires<[UseHVXSgl]>; 385 386 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, 387 VectorRegs128B:$src2, 388 VectorRegs128B:$src3), 389 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, 390 VectorRegs128B:$src2, 391 VectorRegs128B:$src3)>, 392 Requires<[UseHVXDbl]>; 393 } 394 395 multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> { 396 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3), 397 (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>, 398 Requires<[UseHVXSgl]>; 399 400 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 401 VecPredRegs128B:$src2, 402 IntRegs:$src3), 403 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 404 VecPredRegs128B:$src2, 405 IntRegs:$src3)>, 406 Requires<[UseHVXDbl]>; 407 } 408 409 410 multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> { 411 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3), 412 (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, 413 Requires<[UseHVXSgl]>; 414 415 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, 416 VectorRegs128B:$src2, 417 IntRegs:$src3), 418 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, 419 VectorRegs128B:$src2, 420 IntRegs:$src3)>, 421 Requires<[UseHVXDbl]>; 422 } 423 424 multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> { 425 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3), 426 (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>, 427 Requires<[UseHVXSgl]>; 428 429 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 430 VectorRegs128B:$src2, imm:$src3), 431 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 432 VectorRegs128B:$src2, imm:$src3)>, 433 Requires<[UseHVXDbl]>; 434 } 435 436 multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> { 437 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3), 438 (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>, 439 Requires<[UseHVXSgl]>; 440 441 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 442 IntRegs:$src2, imm:$src3), 443 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 444 IntRegs:$src2, imm:$src3)>, 445 Requires<[UseHVXDbl]>; 446 } 447 448 multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> { 449 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4), 450 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>, 451 Requires<[UseHVXSgl]>; 452 453 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 454 VecDblRegs128B:$src2, 455 IntRegs:$src3, imm:$src4), 456 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 457 VecDblRegs128B:$src2, 458 IntRegs:$src3, imm:$src4)>, 459 Requires<[UseHVXDbl]>; 460 } 461 462 multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> { 463 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, 464 IntRegs:$src4), 465 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, 466 IntRegs:$src4)>, 467 Requires<[UseHVXSgl]>; 468 469 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, 470 VectorRegs128B:$src2, 471 VectorRegs128B:$src3, 472 IntRegs:$src4), 473 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, 474 VectorRegs128B:$src2, 475 VectorRegs128B:$src3, 476 IntRegs:$src4)>, 477 Requires<[UseHVXDbl]>; 478 } 479 480 multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> { 481 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, 482 IntRegs:$src4), 483 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, 484 IntRegs:$src4)>, 485 Requires<[UseHVXSgl]>; 486 487 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, 488 VectorRegs128B:$src2, 489 VectorRegs128B:$src3, 490 IntRegs:$src4), 491 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, 492 VectorRegs128B:$src2, 493 VectorRegs128B:$src3, 494 IntRegs:$src4)>, 495 Requires<[UseHVXDbl]>; 496 } 497 498 defm : T_WR_pat<V6_vtmpyb, int_hexagon_V6_vtmpyb>; 499 defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>; 500 defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>; 501 defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>; 502 defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>; 503 defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>; 504 defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>; 505 defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>; 506 defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>; 507 defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>; 508 defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>; 509 defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>; 510 defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>; 511 defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>; 512 defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>; 513 defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>; 514 defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>; 515 defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>; 516 defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>; 517 defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>; 518 defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>; 519 defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>; 520 defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>; 521 defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>; 522 defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>; 523 defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>; 524 defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>; 525 defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>; 526 defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>; 527 defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>; 528 defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>; 529 defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>; 530 531 defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>; 532 defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>; 533 defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>; 534 defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>; 535 defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>; 536 defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>; 537 defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>; 538 defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>; 539 defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>; 540 defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>; 541 defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>; 542 defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>; 543 defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>; 544 defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>; 545 defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>; 546 defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>; 547 defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>; 548 defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>; 549 defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>; 550 defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>; 551 defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>; 552 defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>; 553 defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>; 554 defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>; 555 defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>; 556 defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>; 557 defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>; 558 defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>; 559 defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>; 560 defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>; 561 defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>; 562 defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>; 563 defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>; 564 defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>; 565 defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>; 566 defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>; 567 defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>; 568 defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>; 569 defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>; 570 defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>; 571 defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>; 572 defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>; 573 defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>; 574 defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>; 575 defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>; 576 defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>; 577 defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>; 578 defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>; 579 defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>; 580 defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>; 581 defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>; 582 defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>; 583 defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>; 584 defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>; 585 defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>; 586 defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>; 587 defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>; 588 defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>; 589 defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>; 590 defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>; 591 defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>; 592 defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>; 593 defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>; 594 defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>; 595 596 defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>; 597 defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>; 598 defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>; 599 defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>; 600 defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>; 601 defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>; 602 defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>; 603 defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>; 604 defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>; 605 defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>; 606 defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>; 607 608 defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>; 609 defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>; 610 611 defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>; 612 defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>; 613 defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>; 614 defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>; 615 616 defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>; 617 defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>; 618 defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>; 619 defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>; 620 defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>; 621 defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>; 622 defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>; 623 defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>; 624 625 defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>; 626 defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>; 627 defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>; 628 defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>; 629 defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>; 630 defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>; 631 defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>; 632 defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>; 633 defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>; 634 defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>; 635 defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>; 636 defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>; 637 defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>; 638 defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>; 639 defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>; 640 641 // Compare instructions 642 defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>; 643 defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>; 644 defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>; 645 defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>; 646 defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>; 647 defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>; 648 defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>; 649 defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>; 650 defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>; 651 defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>; 652 defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>; 653 defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>; 654 defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>; 655 defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>; 656 defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>; 657 defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>; 658 defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>; 659 defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>; 660 defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>; 661 defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>; 662 defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>; 663 defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>; 664 defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>; 665 defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>; 666 defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>; 667 defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>; 668 defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>; 669 670 defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>; 671 defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>; 672 defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>; 673 defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>; 674 defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>; 675 defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>; 676 defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>; 677 defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>; 678 defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>; 679 defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>; 680 defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>; 681 defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>; 682 defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>; 683 defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>; 684 defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>; 685 defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>; 686 defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>; 687 defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>; 688 defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>; 689 defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>; 690 defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>; 691 defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>; 692 defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>; 693 defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>; 694 defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>; 695 defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>; 696 defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>; 697 defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>; 698 defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>; 699 defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>; 700 defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>; 701 defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>; 702 defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>; 703 defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>; 704 defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>; 705 defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>; 706 defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>; 707 defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>; 708 defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>; 709 defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>; 710 defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>; 711 defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>; 712 defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>; 713 defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>; 714 defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>; 715 defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>; 716 717 defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>; 718 defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>; 719 defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>; 720 defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>; 721 defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>; 722 defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>; 723 defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>; 724 defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>; 725 defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>; 726 defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>; 727 defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>; 728 defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>; 729 730 defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>; 731 defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>; 732 defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>; 733 defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>; 734 defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>; 735 defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>; 736 defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>; 737 defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>; 738 defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>; 739 defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>; 740 defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>; 741 defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>; 742 defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>; 743 defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>; 744 defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>; 745 defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>; 746 defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>; 747 defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>; 748 defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>; 749 defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>; 750 defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>; 751 defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>; 752 defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>; 753 754 defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>; 755 defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>; 756 defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>; 757 758 defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>; 759 defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>; 760 defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>; 761 762 // assembler mapped. 763 //defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>; 764 // not present earlier.. need to add intrinsic 765 defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>; 766 defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>; 767 defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>; 768 defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>; 769 defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>; 770 defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>; 771 defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>; 772 defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>; 773 defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>; 774 775 defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>; 776 defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>; 777 778 defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>; 779 defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>; 780 defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>; 781 defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>; 782 783 defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>; 784 defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>; 785 defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>; 786 defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>; 787 defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>; 788 defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>; 789 defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>; 790 defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>; 791 defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>; 792 defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>; 793 defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>; 794 defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>; 795 defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>; 796 defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>; 797 defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>; 798 defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>; 799 defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>; 800 801 defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>; 802 defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>; 803 defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>; 804 defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>; 805 defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>; 806 defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>; 807 808 defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>; 809 defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>; 810 defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>; 811 defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>; 812 813 defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>; 814 def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>; 815 def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>; 816 def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>; 817 def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>; 818 def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>; 819 def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>; 820 def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>; 821 def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>; 822 def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>; 823 def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>; 824 def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>; 825 def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>; 826 827 defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>; 828 defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>; 829 830 def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>; 831 832 def: Pat<(v64i16 (trunc v64i32:$Vdd)), 833 (v64i16 (V6_vpackwh_sat_128B 834 (v32i32 (HEXAGON_V6_hi_128B VecDblRegs128B:$Vdd)), 835 (v32i32 (HEXAGON_V6_lo_128B VecDblRegs128B:$Vdd))))>, 836 Requires<[UseHVXDbl]>; 837 838 839
