1 //===- MicroMipsDSPInstrInfo.td - Micromips DSP instructions -*- tablegen *-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes MicroMips DSP instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Instruction encoding. 15 class ADDQ_PH_MM_ENC : POOL32A_3R_FMT<"addq.ph", 0b00000001101>; 16 class ADDQ_S_PH_MM_ENC : POOL32A_3R_FMT<"addq_s.ph", 0b10000001101>; 17 class ADDQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"addq_s.w", 0b1100000101>; 18 class ADDQH_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh.ph", 0b00001001101>; 19 class ADDQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.ph", 0b10001001101>; 20 class ADDQH_W_MMR2_ENC: POOL32A_3R_FMT<"addqh.w", 0b00010001101>; 21 class ADDQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.w", 0b10010001101>; 22 class ADDU_PH_MMR2_ENC : POOL32A_3R_FMT<"addu.ph", 0b00100001101>; 23 class ADDU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"addu_s.ph", 0b10100001101>; 24 class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>; 25 class ADDU_S_QB_MM_ENC : POOL32A_3R_FMT<"addu_s.qb", 0b10011001101>; 26 class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>; 27 class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>; 28 class ADDSC_MM_ENC : POOL32A_3RB0_FMT<"addsc", 0b1110000101>; 29 class ADDWC_MM_ENC : POOL32A_3RB0_FMT<"addwc", 0b1111000101>; 30 class DPA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpa.w.ph", 0b00000010>; 31 class DPAQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpaq_s.w.ph", 0b00001010>; 32 class DPAQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpaq_sa.l.w", 0b01001010>; 33 class DPAQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpaqx_s.w.ph", 0b10001010>; 34 class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpaqx_sa.w.ph", 0b11001010>; 35 class DPAU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpau.h.qbl", 0b10000010>; 36 class DPAU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpau.h.qbr", 0b11000010>; 37 class DPAX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpax.w.ph", 0b01000010>; 38 class ABSQ_S_PH_MM_ENC : POOL32A_2R_FMT<"absq_s.ph", 0b0001000100>; 39 class ABSQ_S_W_MM_ENC : POOL32A_2R_FMT<"absq_s.w", 0b0010000100>; 40 class ABSQ_S_QB_MMR2_ENC : POOL32A_2R_FMT<"absq_s.qb", 0b0000000100>; 41 class INSV_MM_ENC : POOL32A_2R_FMT<"insv", 0b0100000100>; 42 class MADD_DSP_MM_ENC : POOL32A_2RAC_FMT<"madd", 0b00101010>; 43 class MADDU_DSP_MM_ENC : POOL32A_2RAC_FMT<"maddu", 0b01101010>; 44 class MSUB_DSP_MM_ENC : POOL32A_2RAC_FMT<"msub", 0b10101010>; 45 class MSUBU_DSP_MM_ENC : POOL32A_2RAC_FMT<"msubu", 0b11101010>; 46 class MULT_DSP_MM_ENC : POOL32A_2RAC_FMT<"mult", 0b00110010>; 47 class MULTU_DSP_MM_ENC : POOL32A_2RAC_FMT<"multu", 0b01110010>; 48 class SHLL_PH_MM_ENC : POOL32A_2RSA4_FMT<"shll.ph", 0b001110110101>; 49 class SHLL_S_PH_MM_ENC : POOL32A_2RSA4_FMT<"shll_s.ph", 0b101110110101>; 50 class SHLL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shll.qb", 0b0100001>; 51 class SHLLV_PH_MM_ENC : POOL32A_3R_FMT<"shllv.ph", 0b00000001110>; 52 class SHLLV_S_PH_MM_ENC : POOL32A_3R_FMT<"shllv_s.ph", 0b10000001110>; 53 class SHLLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shllv.qb", 0b1110010101>; 54 class SHLLV_S_W_MM_ENC : POOL32A_3RB0_FMT<"shllv_s.w", 0b1111010101>; 55 class SHLL_S_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shll_s.w", 0b1111110101>; 56 class SHRA_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra.qb", 0b0000111>; 57 class SHRA_R_QB_MMR2_ENC : POOL32A_2RSA3_FMT<"shra_r.qb", 0b1000111>; 58 class SHRA_PH_MM_ENC : POOL32A_2RSA4B0_FMT<"shra.ph", 0b01100110101>; 59 class SHRA_R_PH_MM_ENC : POOL32A_2RSA4B0_FMT<"shra_r.ph", 0b11100110101>; 60 class SHRAV_PH_MM_ENC : POOL32A_3R_FMT<"shrav.ph", 0b00110001101>; 61 class SHRAV_R_PH_MM_ENC : POOL32A_3R_FMT<"shrav_r.ph", 0b10110001101>; 62 class SHRAV_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav.qb", 0b00111001101>; 63 class SHRAV_R_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav_r.qb", 0b10111001101>; 64 class SHRAV_R_W_MM_ENC : POOL32A_3RB0_FMT<"shrav_r.w", 0b1011010101>; 65 class SHRA_R_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shra_r.w", 0b1011110101>; 66 class SHRL_PH_MMR2_ENC : POOL32A_2RSA4OP6_FMT<"shrl.ph", 0b001111>; 67 class SHRL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shrl.qb", 0b1100001>; 68 class SHRLV_PH_MMR2_ENC : POOL32A_3RB0_FMT<"shrlv.ph", 0b1100010101>; 69 class SHRLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shrlv.qb", 0b1101010101>; 70 class PRECEQ_W_PHL_MM_ENC : POOL32A_2R_FMT<"preceq.w.phl", 0b0101000100>; 71 class PRECEQ_W_PHR_MM_ENC : POOL32A_2R_FMT<"preceq.w.phr", 0b0110000100>; 72 class PRECEQU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbl", 0b0111000100>; 73 class PRECEQU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbla", 0b0111001100>; 74 class PRECEQU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbr", 0b1001000100>; 75 class PRECEQU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbra", 0b1001001100>; 76 class PRECEU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbl", 0b1011000100>; 77 class PRECEU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbla", 0b1011001100>; 78 class PRECEU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbr", 0b1101000100>; 79 class PRECEU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbra", 0b1101001100>; 80 class SUBQ_PH_MM_ENC : POOL32A_3R_FMT<"subq.ph", 0b01000001101>; 81 class SUBQ_S_PH_MM_ENC : POOL32A_3R_FMT<"subq_s.ph", 0b11000001101>; 82 class SUBQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"subq_s.w", 0b1101000101>; 83 class SUBQH_PH_MMR2_ENC : POOL32A_3R_FMT<"subqh.ph", 0b01001001101>; 84 class SUBQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"subqh_r.ph", 0b11001001101>; 85 class SUBQH_W_MMR2_ENC : POOL32A_3R_FMT<"subqh.w", 0b01010001101>; 86 class SUBQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"subqh_r.w", 0b11010001101>; 87 class SUBU_PH_MMR2_ENC : POOL32A_3R_FMT<"subu.ph", 0b01100001101>; 88 class SUBU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"subu_s.ph", 0b11100001101>; 89 class SUBU_QB_MM_ENC : POOL32A_3R_FMT<"subu.qb", 0b01011001101>; 90 class SUBU_S_QB_MM_ENC : POOL32A_3R_FMT<"subu_s.qb", 0b11011001101>; 91 class SUBUH_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh.qb", 0b01101001101>; 92 class SUBUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh_r.qb", 0b11101001101>; 93 class EXTP_MM_ENC : POOL32A_1RIMM5AC_FMT<"extp", 0b10011001>; 94 class EXTPDP_MM_ENC : POOL32A_1RIMM5AC_FMT<"extpdp", 0b11011001>; 95 class EXTPDPV_MM_ENC : POOL32A_2RAC_FMT<"extpdpv", 0b11100010>; 96 class EXTPV_MM_ENC : POOL32A_2RAC_FMT<"extpv", 0b10100010>; 97 class EXTR_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr.w", 0b00111001>; 98 class EXTR_R_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_r.w", 0b01111001>; 99 class EXTR_RS_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_rs.w", 0b10111001>; 100 class EXTR_S_H_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_s.h", 0b11111001>; 101 class EXTRV_W_MM_ENC : POOL32A_2RAC_FMT<"extrv.w", 0b00111010>; 102 class EXTRV_R_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_r.w", 0b01111010>; 103 class EXTRV_RS_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_rs.w", 0b10111010>; 104 class EXTRV_S_H_MM_ENC : POOL32A_2RAC_FMT<"extrv_s.h", 0b11111010>; 105 class DPS_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dps.w.ph", 0b00010010>; 106 class DPSQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpsq_s.w.ph", 0b00011010>; 107 class DPSQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpsq_sa.l.w", 0b01011010>; 108 class DPSQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_s.w.ph", 0b10011010>; 109 class DPSQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_sa.w.ph", 0b11011010>; 110 class DPSU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbl", 0b10010010>; 111 class DPSU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbr", 0b11010010>; 112 class DPSX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsx.w.ph", 0b01010010>; 113 class MUL_PH_MMR2_ENC : POOL32A_3R_FMT<"mul.ph", 0b00000101101>; 114 class MUL_S_PH_MMR2_ENC : POOL32A_3R_FMT<"mul_s.ph", 0b10000101101>; 115 class MULEQ_S_W_PHL_MM_ENC : POOL32A_3RB0_FMT<"muleq_s.w.phl", 0b0000100101>; 116 class MULEQ_S_W_PHR_MM_ENC : POOL32A_3RB0_FMT<"muleq_s.w.phr", 0b0001100101>; 117 class MULEU_S_PH_QBL_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbl", 0b0010010101>; 118 class MULEU_S_PH_QBR_MM_ENC : POOL32A_3RB0_FMT<"muleu_s.ph.qbr", 0b0011010101>; 119 class MULQ_RS_PH_MM_ENC : POOL32A_3RB0_FMT<"mulq_rs.ph", 0b0100010101>; 120 class MULQ_RS_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_rs.w", 0b0110010101>; 121 class MULQ_S_PH_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.ph", 0b0101010101>; 122 class MULQ_S_W_MMR2_ENC : POOL32A_3RB0_FMT<"mulq_s.w", 0b0111010101>; 123 class PRECR_QB_PH_MMR2_ENC : POOL32A_3RB0_FMT<"precr.qb.ph", 0b0001101101>; 124 class PRECR_SRA_PH_W_MMR2_ENC 125 : POOL32A_2RSA5_FMT<"precr_sra.ph.w", 0b01111001101>; 126 class PRECR_SRA_R_PH_W_MMR2_ENC 127 : POOL32A_2RSA5_FMT<"precr_sra_r.ph.w", 0b11111001101>; 128 class PRECRQ_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq.ph.w", 0b0011101101>; 129 class PRECRQ_QB_PH_MM_ENC : POOL32A_3RB0_FMT<"precrq.qb.ph", 0b0010101101>; 130 class PRECRQU_S_QB_PH_MM_ENC 131 : POOL32A_3RB0_FMT<"precrqu_s.qb.ph", 0b0101101101>; 132 class PRECRQ_RS_PH_W_MM_ENC : POOL32A_3RB0_FMT<"precrq_rs.ph.w", 0b0100101101>; 133 class LBUX_MM_ENC : POOL32A_1RMEMB0_FMT<"lbux", 0b1000100101>; 134 class LHX_MM_ENC : POOL32A_1RMEMB0_FMT<"lhx", 0b0101100101>; 135 class LWX_MM_ENC : POOL32A_1RMEMB0_FMT<"lwx", 0b0110100101>; 136 class MAQ_S_W_PHL_MM_ENC : POOL32A_2RAC_FMT<"maq_s.w.phl", 0b01101001>; 137 class MAQ_SA_W_PHL_MM_ENC : POOL32A_2RAC_FMT<"maq_sa.w.phl", 0b11101001>; 138 class MAQ_S_W_PHR_MM_ENC : POOL32A_2RAC_FMT<"maq_s.w.phr", 0b00101001>; 139 class MAQ_SA_W_PHR_MM_ENC : POOL32A_2RAC_FMT<"maq_sa.w.phr", 0b10101001>; 140 class MFHI_MM_ENC : POOL32A_1RAC_FMT<"mfhi", 0b00000001>; 141 class MFLO_MM_ENC : POOL32A_1RAC_FMT<"mflo", 0b01000001>; 142 class MTHI_MM_ENC : POOL32A_1RAC_FMT<"mthi", 0b10000001>; 143 class MTLO_MM_ENC : POOL32A_1RAC_FMT<"mthi", 0b11000001>; 144 class PREPEND_MMR2_ENC : POOL32A_2RSA5B0_FMT<"prepend", 0b1001010101>; 145 class RADDU_W_QB_MM_ENC : POOL32A_2R_FMT<"raddu.w.qb", 0b1111000100>; 146 class RDDSP_MM_ENC : POOL32A_1RMASK7_FMT<"rddsp", 0b00011001>; 147 class REPL_PH_MM_ENC : POOL32A_1RIMM10_FMT<"repl.ph", 0b0000111101>; 148 class REPL_QB_MM_ENC : POOL32A_1RIMM8_FMT<"repl.qb", 0b010111>; 149 class REPLV_PH_MM_ENC : POOL32A_2R_FMT<"replv.ph", 0b0000001100>; 150 class REPLV_QB_MM_ENC : POOL32A_2R_FMT<"replv.qb", 0b0001001100>; 151 class MTHLIP_MM_ENC : POOL32A_1RAC_FMT<"mthlip", 0b00001001>; 152 class PACKRL_PH_MM_ENC : POOL32A_3RB0_FMT<"packrl.ph", 0b0110101101>; 153 class PICK_PH_MM_ENC : POOL32A_3RB0_FMT<"pick.ph", 0b1000101101>; 154 class PICK_QB_MM_ENC : POOL32A_3RB0_FMT<"pick.qb", 0b0111101101>; 155 class SHILO_MM_ENC : POOL32A_4B0SHIFT6AC4B0_FMT<"shilo", 0b0000011101>; 156 class SHILOV_MM_ENC : POOL32A_5B01RAC_FMT<"shilov", 0b01001001>; 157 class WRDSP_MM_ENC : POOL32A_1RMASK7_FMT<"wrdsp", 0b01011001>; 158 class APPEND_MMR2_ENC : POOL32A_2RSA5B0_FMT<"append", 0b1000010101>; 159 class MODSUB_MM_ENC : POOL32A_3RB0_FMT<"modsub", 0b1010010101>; 160 class MULSA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"mulsa.w.ph", 0b10110010>; 161 class MULSAQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"mulsaq_s.w.ph", 0b11110010>; 162 class BPOSGE32C_MMR3_ENC : POOL32I_IMMB0_FMT<"bposge32c", 0b11001>; 163 class BITREV_MM_ENC : POOL32A_2R_FMT<"bitrev", 0b0011000100>; 164 class BALIGN_MMR2_ENC : POOL32A_2RBP_FMT<"balign">; 165 class BPOSGE32_MM_ENC : POOL32I_IMMB0_FMT<"bposge32", 0b11011>; 166 class CMP_EQ_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.eq.ph", 0b0000000101>; 167 class CMP_LE_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.le.ph", 0b0010000101>; 168 class CMP_LT_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.lt.ph", 0b0001000101>; 169 class CMPGDU_EQ_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.eq.qb", 0b0110000101>; 170 class CMPGDU_LT_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.lt.qb", 0b0111000101>; 171 class CMPGDU_LE_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.le.qb", 0b1000000101>; 172 class CMPGU_EQ_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.eq.qb", 0b0011000101>; 173 class CMPGU_LT_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.lt.qb", 0b0100000101>; 174 class CMPGU_LE_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.le.qb", 0b0101000101>; 175 class CMPU_EQ_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.eq.qb", 0b1001000101>; 176 class CMPU_LT_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.lt.qb", 0b1010000101>; 177 class CMPU_LE_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.le.qb", 0b1011000101>; 178 179 // Instruction desc. 180 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode, 181 InstrItinClass itin, RegisterOperand ROD, 182 RegisterOperand ROS = ROD> { 183 dag OutOperandList = (outs ROD:$rt); 184 dag InOperandList = (ins ROS:$rs); 185 string AsmString = !strconcat(opstr, "\t$rt, $rs"); 186 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))]; 187 InstrItinClass Itinerary = itin; 188 } 189 class ABSQ_S_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 190 "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>; 191 class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 192 "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>; 193 class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 194 "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>; 195 class PRECEQ_W_PHL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 196 "preceq.w.phl", int_mips_preceq_w_phl, NoItinerary, GPR32Opnd, DSPROpnd>; 197 class PRECEQ_W_PHR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 198 "preceq.w.phr", int_mips_preceq_w_phr, NoItinerary, GPR32Opnd, DSPROpnd>; 199 class PRECEQU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 200 "precequ.ph.qbl", int_mips_precequ_ph_qbl, NoItinerary, DSPROpnd>; 201 class PRECEQU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 202 "precequ.ph.qbla", int_mips_precequ_ph_qbla, NoItinerary, DSPROpnd>; 203 class PRECEQU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 204 "precequ.ph.qbr", int_mips_precequ_ph_qbr, NoItinerary, DSPROpnd>; 205 class PRECEQU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 206 "precequ.ph.qbra", int_mips_precequ_ph_qbra, NoItinerary, DSPROpnd>; 207 class PRECEU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 208 "preceu.ph.qbl", int_mips_preceu_ph_qbl, NoItinerary, DSPROpnd>; 209 class PRECEU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 210 "preceu.ph.qbla", int_mips_preceu_ph_qbla, NoItinerary, DSPROpnd>; 211 class PRECEU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 212 "preceu.ph.qbr", int_mips_preceu_ph_qbr, NoItinerary, DSPROpnd>; 213 class PRECEU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< 214 "preceu.ph.qbra", int_mips_preceu_ph_qbra, NoItinerary, DSPROpnd>; 215 216 class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 217 SDPatternOperator ImmPat, InstrItinClass itin, 218 RegisterOperand RO, Operand ImmOpnd> { 219 dag OutOperandList = (outs RO:$rt); 220 dag InOperandList = (ins RO:$rs, ImmOpnd:$sa); 221 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); 222 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))]; 223 InstrItinClass Itinerary = itin; 224 bit hasSideEffects = 1; 225 } 226 class SHLL_PH_MM_DESC : SHLL_R2_MM_DESC_BASE< 227 "shll.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>, 228 Defs<[DSPOutFlag22]>; 229 class SHLL_S_PH_MM_DESC : SHLL_R2_MM_DESC_BASE< 230 "shll_s.ph", int_mips_shll_s_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>, 231 Defs<[DSPOutFlag22]>; 232 class SHLL_QB_MM_DESC : SHLL_R2_MM_DESC_BASE< 233 "shll.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>, 234 Defs<[DSPOutFlag22]>; 235 class SHLL_S_W_MM_DESC : SHLL_R2_MM_DESC_BASE< 236 "shll_s.w", int_mips_shll_s_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>, 237 Defs<[DSPOutFlag22]>; 238 class SHRA_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE< 239 "shra.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>; 240 class SHRA_R_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE< 241 "shra_r.qb", int_mips_shra_r_qb, immZExt3, NoItinerary, DSPROpnd, uimm3>; 242 class SHRA_PH_MM_DESC : SHLL_R2_MM_DESC_BASE< 243 "shra.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>; 244 class SHRA_R_PH_MM_DESC : SHLL_R2_MM_DESC_BASE< 245 "shra_r.ph", int_mips_shra_r_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>; 246 class SHRA_R_W_MM_DESC : SHLL_R2_MM_DESC_BASE< 247 "shra_r.w", int_mips_shra_r_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>; 248 class SHRL_QB_MM_DESC : SHLL_R2_MM_DESC_BASE< 249 "shrl.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>; 250 class SHRL_PH_MMR2_DESC : SHLL_R2_MM_DESC_BASE< 251 "shrl.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>; 252 253 class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 254 InstrItinClass itin, RegisterOperand RO> { 255 dag OutOperandList = (outs RO:$rd); 256 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs); 257 string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs"); 258 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))]; 259 InstrItinClass Itinerary = itin; 260 } 261 class SHLLV_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE< 262 "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>; 263 class SHLLV_S_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE< 264 "shllv_s.ph", int_mips_shll_s_ph, NoItinerary, DSPROpnd>, 265 Defs<[DSPOutFlag22]>; 266 class SHLLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE< 267 "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>; 268 class SHLLV_S_W_MM_DESC : SHLLV_R3_MM_DESC_BASE< 269 "shllv_s.w", int_mips_shll_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag22]>; 270 class SHRAV_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE< 271 "shrav.ph", int_mips_shra_ph, NoItinerary, DSPROpnd>; 272 class SHRAV_R_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE< 273 "shrav_r.ph", int_mips_shra_r_ph, NoItinerary, DSPROpnd>; 274 class SHRAV_QB_MMR2_DESC : SHLLV_R3_MM_DESC_BASE< 275 "shrav.qb", int_mips_shra_qb, NoItinerary, DSPROpnd>; 276 class SHRAV_R_QB_MMR2_DESC : SHLLV_R3_MM_DESC_BASE< 277 "shrav_r.qb", int_mips_shra_r_qb, NoItinerary, DSPROpnd>; 278 class SHRAV_R_W_MM_DESC : SHLLV_R3_MM_DESC_BASE< 279 "shrav_r.w", int_mips_shra_r_w, NoItinerary, GPR32Opnd>; 280 class SHRLV_PH_MMR2_DESC : SHLLV_R3_MM_DESC_BASE< 281 "shrlv.ph", int_mips_shrl_ph, NoItinerary, DSPROpnd>; 282 class SHRLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE< 283 "shrlv.qb", int_mips_shrl_qb, NoItinerary, DSPROpnd>; 284 285 class EXT_MM_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 286 InstrItinClass itin> { 287 dag OutOperandList = (outs GPR32Opnd:$rt); 288 dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$rs); 289 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $rs"); 290 InstrItinClass Itinerary = itin; 291 } 292 class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 293 InstrItinClass itin> { 294 dag OutOperandList = (outs GPR32Opnd:$rt); 295 dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$imm); 296 string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $imm"); 297 InstrItinClass Itinerary = itin; 298 } 299 300 class EXTP_MM_DESC 301 : EXT_MM_1R_DESC_BASE<"extp", MipsEXTP, NoItinerary>, 302 Uses<[DSPPos]>, Defs<[DSPEFI]>; 303 class EXTPDP_MM_DESC 304 : EXT_MM_1R_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>, 305 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>; 306 class EXTPDPV_MM_DESC 307 : EXT_MM_2R_DESC_BASE<"extpdpv", MipsEXTPDP, NoItinerary>, 308 Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>; 309 class EXTPV_MM_DESC 310 : EXT_MM_2R_DESC_BASE<"extpv", MipsEXTP, NoItinerary>, 311 Uses<[DSPPos]>, Defs<[DSPEFI]>; 312 class EXTR_W_MM_DESC 313 : EXT_MM_1R_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>, 314 Defs<[DSPOutFlag23]>; 315 class EXTR_R_W_MM_DESC 316 : EXT_MM_1R_DESC_BASE<"extr_r.w", MipsEXTR_R_W, NoItinerary>, 317 Defs<[DSPOutFlag23]>; 318 class EXTR_RS_W_MM_DESC 319 : EXT_MM_1R_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W, NoItinerary>, 320 Defs<[DSPOutFlag23]>; 321 class EXTR_S_H_MM_DESC 322 : EXT_MM_1R_DESC_BASE<"extr_s.h", MipsEXTR_S_H, NoItinerary>, 323 Defs<[DSPOutFlag23]>; 324 class EXTRV_W_MM_DESC 325 : EXT_MM_2R_DESC_BASE<"extrv.w", MipsEXTR_W, NoItinerary>, 326 Defs<[DSPOutFlag23]>; 327 class EXTRV_R_W_MM_DESC 328 : EXT_MM_2R_DESC_BASE<"extrv_r.w", MipsEXTR_R_W, NoItinerary>, 329 Defs<[DSPOutFlag23]>; 330 class EXTRV_RS_W_MM_DESC 331 : EXT_MM_2R_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W, NoItinerary>, 332 Defs<[DSPOutFlag23]>; 333 class EXTRV_S_H_MM_DESC 334 : EXT_MM_2R_DESC_BASE<"extrv_s.h", MipsEXTR_S_H, NoItinerary>, 335 Defs<[DSPOutFlag23]>; 336 337 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode, 338 InstrItinClass itin> { 339 dag OutOperandList = (outs GPR32Opnd:$rs); 340 dag InOperandList = (ins RO:$ac); 341 string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); 342 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))]; 343 InstrItinClass Itinerary = itin; 344 } 345 346 class MFHI_MM_DESC : MFHI_MM_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, 347 NoItinerary>; 348 class MFLO_MM_DESC : MFHI_MM_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, 349 NoItinerary>; 350 351 class RADDU_W_QB_MM_DESC { 352 dag OutOperandList = (outs GPR32Opnd:$rt); 353 dag InOperandList = (ins DSPROpnd:$rs); 354 string AsmString = !strconcat("raddu.w.qb", "\t$rt, $rs"); 355 list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_raddu_w_qb DSPROpnd:$rs))]; 356 InstrItinClass Itinerary = NoItinerary; 357 string BaseOpcode = "raddu.w.qb"; 358 } 359 360 class RDDSP_MM_DESC { 361 dag OutOperandList = (outs GPR32Opnd:$rt); 362 dag InOperandList = (ins uimm7:$mask); 363 string AsmString = !strconcat("rddsp", "\t$rt, $mask"); 364 list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_rddsp immZExt7:$mask))]; 365 InstrItinClass Itinerary = NoItinerary; 366 } 367 368 class REPL_QB_MM_DESC { 369 dag OutOperandList = (outs DSPROpnd:$rt); 370 dag InOperandList = (ins uimm8:$imm); 371 string AsmString = !strconcat("repl.qb", "\t$rt, $imm"); 372 list<dag> Pattern = [(set DSPROpnd:$rt, (int_mips_repl_qb immZExt8:$imm))]; 373 InstrItinClass Itinerary = NoItinerary; 374 } 375 376 class REPLV_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.ph", int_mips_repl_ph, 377 NoItinerary, DSPROpnd, 378 GPR32Opnd>; 379 class REPLV_QB_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.qb", int_mips_repl_qb, 380 NoItinerary, DSPROpnd, 381 GPR32Opnd>; 382 383 class WRDSP_MM_DESC { 384 dag OutOperandList = (outs); 385 dag InOperandList = (ins GPR32Opnd:$rt, uimm7:$mask); 386 string AsmString = !strconcat("wrdsp", "\t$rt, $mask"); 387 list<dag> Pattern = [(int_mips_wrdsp GPR32Opnd:$rt, immZExt7:$mask)]; 388 InstrItinClass Itinerary = NoItinerary; 389 } 390 391 class BPOSGE32C_MMR3_DESC { 392 dag OutOperandList = (outs); 393 dag InOperandList = (ins brtarget1SImm16:$offset); 394 string AsmString = !strconcat("bposge32c", "\t$offset"); 395 InstrItinClass Itinerary = NoItinerary; 396 bit isBranch = 1; 397 bit isTerminator = 1; 398 bit hasDelaySlot = 0; 399 } 400 401 class BALIGN_MMR2_DESC { 402 dag OutOperandList = (outs GPR32Opnd:$rt); 403 dag InOperandList = (ins GPR32Opnd:$rs, uimm2:$bp, GPR32Opnd:$src); 404 string AsmString = !strconcat("balign", "\t$rt, $rs, $bp"); 405 list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_balign GPR32Opnd:$src, 406 GPR32Opnd:$rs, 407 immZExt2:$bp))]; 408 InstrItinClass Itinerary = NoItinerary; 409 string Constraints = "$src = $rt"; 410 } 411 412 class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev, 413 NoItinerary, GPR32Opnd>; 414 415 class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm, 416 NoItinerary>; 417 418 // Instruction defs. 419 // microMIPS DSP Rev 1 420 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC; 421 def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC; 422 def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC; 423 def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC; 424 def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC; 425 def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC; 426 def ADDWC_MM : DspMMRel, ADDWC_MM_ENC, ADDWC_DESC; 427 def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC; 428 def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC; 429 def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC; 430 def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC; 431 def ABSQ_S_PH_MM : DspMMRel, ABSQ_S_PH_MM_ENC, ABSQ_S_PH_MM_DESC; 432 def ABSQ_S_W_MM : DspMMRel, ABSQ_S_W_MM_ENC, ABSQ_S_W_MM_DESC; 433 def INSV_MM : DspMMRel, INSV_MM_ENC, INSV_DESC; 434 def MADD_DSP_MM : DspMMRel, MADD_DSP_MM_ENC, MADD_DSP_DESC; 435 def MADDU_DSP_MM : DspMMRel, MADDU_DSP_MM_ENC, MADDU_DSP_DESC; 436 def MSUB_DSP_MM : DspMMRel, MSUB_DSP_MM_ENC, MSUB_DSP_DESC; 437 def MSUBU_DSP_MM : DspMMRel, MSUBU_DSP_MM_ENC, MSUBU_DSP_DESC; 438 def MULT_DSP_MM : DspMMRel, MULT_DSP_MM_ENC, MULT_DSP_DESC; 439 def MULTU_DSP_MM : DspMMRel, MULTU_DSP_MM_ENC, MULTU_DSP_DESC; 440 def SHLL_PH_MM : DspMMRel, SHLL_PH_MM_ENC, SHLL_PH_MM_DESC; 441 def SHLL_S_PH_MM : DspMMRel, SHLL_S_PH_MM_ENC, SHLL_S_PH_MM_DESC; 442 def SHLL_QB_MM : DspMMRel, SHLL_QB_MM_ENC, SHLL_QB_MM_DESC; 443 def SHLLV_PH_MM : DspMMRel, SHLLV_PH_MM_ENC, SHLLV_PH_MM_DESC; 444 def SHLLV_S_PH_MM : DspMMRel, SHLLV_S_PH_MM_ENC, SHLLV_S_PH_MM_DESC; 445 def SHLLV_QB_MM : DspMMRel, SHLLV_QB_MM_ENC, SHLLV_QB_MM_DESC; 446 def SHLLV_S_W_MM : DspMMRel, SHLLV_S_W_MM_ENC, SHLLV_S_W_MM_DESC; 447 def SHLL_S_W_MM : DspMMRel, SHLL_S_W_MM_ENC, SHLL_S_W_MM_DESC; 448 def SHRA_PH_MM : DspMMRel, SHRA_PH_MM_ENC, SHRA_PH_MM_DESC; 449 def SHRA_R_PH_MM : DspMMRel, SHRA_R_PH_MM_ENC, SHRA_R_PH_MM_DESC; 450 def SHRAV_PH_MM : DspMMRel, SHRAV_PH_MM_ENC, SHRAV_PH_MM_DESC; 451 def SHRAV_R_PH_MM : DspMMRel, SHRAV_R_PH_MM_ENC, SHRAV_R_PH_MM_DESC; 452 def SHRAV_R_W_MM : DspMMRel, SHRAV_R_W_MM_ENC, SHRAV_R_W_MM_DESC; 453 def SHRA_R_W_MM : DspMMRel, SHRA_R_W_MM_ENC, SHRA_R_W_MM_DESC; 454 def SHRL_QB_MM : DspMMRel, SHRL_QB_MM_ENC, SHRL_QB_MM_DESC; 455 def SHRLV_QB_MM : DspMMRel, SHRLV_QB_MM_ENC, SHRLV_QB_MM_DESC; 456 def PRECEQ_W_PHL_MM : DspMMRel, PRECEQ_W_PHL_MM_ENC, PRECEQ_W_PHL_MM_DESC; 457 def PRECEQ_W_PHR_MM : DspMMRel, PRECEQ_W_PHR_MM_ENC, PRECEQ_W_PHR_MM_DESC; 458 def PRECEQU_PH_QBL_MM : DspMMRel, PRECEQU_PH_QBL_MM_ENC, PRECEQU_PH_QBL_MM_DESC; 459 def PRECEQU_PH_QBLA_MM : DspMMRel, PRECEQU_PH_QBLA_MM_ENC, 460 PRECEQU_PH_QBLA_MM_DESC; 461 def PRECEQU_PH_QBR_MM : DspMMRel, PRECEQU_PH_QBR_MM_ENC, PRECEQU_PH_QBR_MM_DESC; 462 def PRECEQU_PH_QBRA_MM : DspMMRel, PRECEQU_PH_QBRA_MM_ENC, 463 PRECEQU_PH_QBRA_MM_DESC; 464 def PRECEU_PH_QBL_MM : DspMMRel, PRECEU_PH_QBL_MM_ENC, PRECEU_PH_QBL_MM_DESC; 465 def PRECEU_PH_QBLA_MM : DspMMRel, PRECEU_PH_QBLA_MM_ENC, PRECEU_PH_QBLA_MM_DESC; 466 def PRECEU_PH_QBR_MM : DspMMRel, PRECEU_PH_QBR_MM_ENC, PRECEU_PH_QBR_MM_DESC; 467 def PRECEU_PH_QBRA_MM : DspMMRel, PRECEU_PH_QBRA_MM_ENC, PRECEU_PH_QBRA_MM_DESC; 468 def SUBQ_PH_MM : DspMMRel, SUBQ_PH_MM_ENC, SUBQ_PH_DESC; 469 def SUBQ_S_PH_MM : DspMMRel, SUBQ_S_PH_MM_ENC, SUBQ_S_PH_DESC; 470 def SUBQ_S_W_MM : DspMMRel, SUBQ_S_W_MM_ENC, SUBQ_S_W_DESC; 471 def SUBU_QB_MM : DspMMRel, SUBU_QB_MM_ENC, SUBU_QB_DESC; 472 def SUBU_S_QB_MM : DspMMRel, SUBU_S_QB_MM_ENC, SUBU_S_QB_DESC; 473 def EXTP_MM : DspMMRel, EXTP_MM_ENC, EXTP_MM_DESC; 474 def EXTPDP_MM : DspMMRel, EXTPDP_MM_ENC, EXTPDP_MM_DESC; 475 def EXTPDPV_MM : DspMMRel, EXTPDPV_MM_ENC, EXTPDPV_MM_DESC; 476 def EXTPV_MM : DspMMRel, EXTPV_MM_ENC, EXTPV_MM_DESC; 477 def EXTR_W_MM : DspMMRel, EXTR_W_MM_ENC, EXTR_W_MM_DESC; 478 def EXTR_R_W_MM : DspMMRel, EXTR_R_W_MM_ENC, EXTR_R_W_MM_DESC; 479 def EXTR_RS_W_MM : DspMMRel, EXTR_RS_W_MM_ENC, EXTR_RS_W_MM_DESC; 480 def EXTR_S_H_MM : DspMMRel, EXTR_S_H_MM_ENC, EXTR_S_H_MM_DESC; 481 def EXTRV_W_MM : DspMMRel, EXTRV_W_MM_ENC, EXTRV_W_MM_DESC; 482 def EXTRV_R_W_MM : DspMMRel, EXTRV_R_W_MM_ENC, EXTRV_R_W_MM_DESC; 483 def EXTRV_RS_W_MM : DspMMRel, EXTRV_RS_W_MM_ENC, EXTRV_RS_W_MM_DESC; 484 def EXTRV_S_H_MM : DspMMRel, EXTRV_S_H_MM_ENC, EXTRV_S_H_MM_DESC; 485 def DPSQ_S_W_PH_MM : DspMMRel, DPSQ_S_W_PH_MM_ENC, DPSQ_S_W_PH_DESC; 486 def DPSQ_SA_L_W_MM : DspMMRel, DPSQ_SA_L_W_MM_ENC, DPSQ_SA_L_W_DESC; 487 def DPSU_H_QBL_MM : DspMMRel, DPSU_H_QBL_MM_ENC, DPSU_H_QBL_DESC; 488 def DPSU_H_QBR_MM : DspMMRel, DPSU_H_QBR_MM_ENC, DPSU_H_QBR_DESC; 489 def MULEQ_S_W_PHL_MM : DspMMRel, MULEQ_S_W_PHL_MM_ENC, MULEQ_S_W_PHL_DESC; 490 def MULEQ_S_W_PHR_MM : DspMMRel, MULEQ_S_W_PHR_MM_ENC, MULEQ_S_W_PHR_DESC; 491 def MULEU_S_PH_QBL_MM : DspMMRel, MULEU_S_PH_QBL_MM_ENC, MULEU_S_PH_QBL_DESC; 492 def MULEU_S_PH_QBR_MM : DspMMRel, MULEU_S_PH_QBR_MM_ENC, MULEU_S_PH_QBR_DESC; 493 def MULQ_RS_PH_MM : DspMMRel, MULQ_RS_PH_MM_ENC, MULQ_RS_PH_DESC; 494 def PRECRQ_PH_W_MM : DspMMRel, PRECRQ_PH_W_MM_ENC, PRECRQ_PH_W_DESC; 495 def PRECRQ_QB_PH_MM : DspMMRel, PRECRQ_QB_PH_MM_ENC, PRECRQ_QB_PH_DESC; 496 def PRECRQU_S_QB_PH_MM : DspMMRel, PRECRQU_S_QB_PH_MM_ENC, PRECRQU_S_QB_PH_DESC; 497 def PRECRQ_RS_PH_W_MM : DspMMRel, PRECRQ_RS_PH_W_MM_ENC, PRECRQ_RS_PH_W_DESC; 498 def LBUX_MM : DspMMRel, LBUX_MM_ENC, LBUX_DESC; 499 def LHX_MM : DspMMRel, LHX_MM_ENC, LHX_DESC; 500 def LWX_MM : DspMMRel, LWX_MM_ENC, LWX_DESC; 501 def MAQ_S_W_PHL_MM : DspMMRel, MAQ_S_W_PHL_MM_ENC, MAQ_S_W_PHL_DESC; 502 def MAQ_SA_W_PHL_MM : DspMMRel, MAQ_SA_W_PHL_MM_ENC, MAQ_SA_W_PHL_DESC; 503 def MAQ_S_W_PHR_MM : DspMMRel, MAQ_S_W_PHR_MM_ENC, MAQ_S_W_PHR_DESC; 504 def MAQ_SA_W_PHR_MM : DspMMRel, MAQ_SA_W_PHR_MM_ENC, MAQ_SA_W_PHR_DESC; 505 def MFHI_DSP_MM : DspMMRel, MFHI_MM_ENC, MFHI_MM_DESC; 506 def MFLO_DSP_MM : DspMMRel, MFLO_MM_ENC, MFLO_MM_DESC; 507 def MTHI_DSP_MM : DspMMRel, MTHI_MM_ENC, MTHI_DESC; 508 def MTLO_DSP_MM : DspMMRel, MTLO_MM_ENC, MTLO_DESC; 509 def RADDU_W_QB_MM : DspMMRel, RADDU_W_QB_MM_ENC, RADDU_W_QB_MM_DESC; 510 def RDDSP_MM : DspMMRel, RDDSP_MM_ENC, RDDSP_MM_DESC; 511 def REPL_PH_MM : DspMMRel, REPL_PH_MM_ENC, REPL_PH_DESC; 512 def REPL_QB_MM : DspMMRel, REPL_QB_MM_ENC, REPL_QB_MM_DESC; 513 def REPLV_PH_MM : DspMMRel, REPLV_PH_MM_ENC, REPLV_PH_MM_DESC; 514 def REPLV_QB_MM : DspMMRel, REPLV_QB_MM_ENC, REPLV_QB_MM_DESC; 515 def MTHLIP_MM : DspMMRel, MTHLIP_MM_ENC, MTHLIP_DESC; 516 def PACKRL_PH_MM : DspMMRel, PACKRL_PH_MM_ENC, PACKRL_PH_DESC; 517 def PICK_PH_MM : DspMMRel, PICK_PH_MM_ENC, PICK_PH_DESC; 518 def PICK_QB_MM : DspMMRel, PICK_QB_MM_ENC, PICK_QB_DESC; 519 def SHILO_MM : DspMMRel, SHILO_MM_ENC, SHILO_DESC; 520 def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC; 521 def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC; 522 def MODSUB_MM : DspMMRel, MODSUB_MM_ENC, MODSUB_DESC; 523 def MULSAQ_S_W_PH_MM : DspMMRel, MULSAQ_S_W_PH_MM_ENC, MULSAQ_S_W_PH_DESC; 524 def BITREV_MM : DspMMRel, BITREV_MM_ENC, BITREV_MM_DESC; 525 def BPOSGE32_MM : DspMMRel, BPOSGE32_MM_ENC, BPOSGE32_MM_DESC, 526 ISA_MIPS1_NOT_32R6_64R6; 527 def CMP_EQ_PH_MM : DspMMRel, CMP_EQ_PH_MM_ENC, CMP_EQ_PH_DESC; 528 def CMP_LT_PH_MM : DspMMRel, CMP_LT_PH_MM_ENC, CMP_LT_PH_DESC; 529 def CMP_LE_PH_MM : DspMMRel, CMP_LE_PH_MM_ENC, CMP_LE_PH_DESC; 530 def CMPGU_EQ_QB_MM : DspMMRel, CMPGU_EQ_QB_MM_ENC, CMPGU_EQ_QB_DESC; 531 def CMPGU_LT_QB_MM : DspMMRel, CMPGU_LT_QB_MM_ENC, CMPGU_LT_QB_DESC; 532 def CMPGU_LE_QB_MM : DspMMRel, CMPGU_LE_QB_MM_ENC, CMPGU_LE_QB_DESC; 533 def CMPU_EQ_QB_MM : DspMMRel, CMPU_EQ_QB_MM_ENC, CMPU_EQ_QB_DESC; 534 def CMPU_LT_QB_MM : DspMMRel, CMPU_LT_QB_MM_ENC, CMPU_LT_QB_DESC; 535 def CMPU_LE_QB_MM : DspMMRel, CMPU_LE_QB_MM_ENC, CMPU_LE_QB_DESC; 536 // microMIPS DSP Rev 2 537 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, 538 ISA_DSPR2; 539 def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2; 540 def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2; 541 def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2; 542 def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2; 543 def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2; 544 def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2; 545 def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2; 546 def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2; 547 def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2; 548 def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC, 549 ISA_DSPR2; 550 def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC, 551 ISA_DSPR2; 552 def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2; 553 def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2; 554 def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC, 555 ISA_DSPR2; 556 def SHRAV_QB_MMR2 : DspMMRel, SHRAV_QB_MMR2_ENC, SHRAV_QB_MMR2_DESC, ISA_DSPR2; 557 def SHRAV_R_QB_MMR2 : DspMMRel, SHRAV_R_QB_MMR2_ENC, SHRAV_R_QB_MMR2_DESC, 558 ISA_DSPR2; 559 def BALIGN_MMR2 : DspMMRel, BALIGN_MMR2_ENC, BALIGN_MMR2_DESC, ISA_DSPR2; 560 def CMPGDU_EQ_QB_MMR2 : DspMMRel, CMPGDU_EQ_QB_MMR2_ENC, CMPGDU_EQ_QB_DESC, 561 ISA_DSPR2; 562 def CMPGDU_LT_QB_MMR2 : DspMMRel, CMPGDU_LT_QB_MMR2_ENC, CMPGDU_LT_QB_DESC, 563 ISA_DSPR2; 564 def CMPGDU_LE_QB_MMR2 : DspMMRel, CMPGDU_LE_QB_MMR2_ENC, CMPGDU_LE_QB_DESC, 565 ISA_DSPR2; 566 def SHRL_PH_MMR2 : DspMMRel, SHRL_PH_MMR2_ENC, SHRL_PH_MMR2_DESC, ISA_DSPR2; 567 def SHRLV_PH_MMR2 : DspMMRel, SHRLV_PH_MMR2_ENC, SHRLV_PH_MMR2_DESC, ISA_DSPR2; 568 def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2; 569 def SUBQH_R_PH_MMR2 : DspMMRel, SUBQH_R_PH_MMR2_ENC, SUBQH_R_PH_DESC, ISA_DSPR2; 570 def SUBQH_W_MMR2 : DspMMRel, SUBQH_W_MMR2_ENC, SUBQH_W_DESC, ISA_DSPR2; 571 def SUBQH_R_W_MMR2 : DspMMRel, SUBQH_R_W_MMR2_ENC, SUBQH_R_W_DESC, ISA_DSPR2; 572 def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2; 573 def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2; 574 def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2; 575 def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2; 576 def DPS_W_PH_MMR2 : DspMMRel, DPS_W_PH_MMR2_ENC, DPS_W_PH_DESC, ISA_DSPR2; 577 def DPSQX_S_W_PH_MMR2 : DspMMRel, DPSQX_S_W_PH_MMR2_ENC, DPSQX_S_W_PH_DESC, 578 ISA_DSPR2; 579 def DPSQX_SA_W_PH_MMR2 : DspMMRel, DPSQX_SA_W_PH_MMR2_ENC, DPSQX_SA_W_PH_DESC, 580 ISA_DSPR2; 581 def DPSX_W_PH_MMR2 : DspMMRel, DPSX_W_PH_MMR2_ENC, DPSX_W_PH_DESC, ISA_DSPR2; 582 def MUL_PH_MMR2 : DspMMRel, MUL_PH_MMR2_ENC, MUL_PH_DESC, ISA_DSPR2; 583 def MUL_S_PH_MMR2 : DspMMRel, MUL_S_PH_MMR2_ENC, MUL_S_PH_DESC, ISA_DSPR2; 584 def MULQ_RS_W_MMR2 : DspMMRel, MULQ_RS_W_MMR2_ENC, MULQ_RS_W_DESC, ISA_DSPR2; 585 def MULQ_S_PH_MMR2 : DspMMRel, MULQ_S_PH_MMR2_ENC, MULQ_S_PH_DESC, ISA_DSPR2; 586 def MULQ_S_W_MMR2 : DspMMRel, MULQ_S_W_MMR2_ENC, MULQ_S_W_DESC, ISA_DSPR2; 587 def PRECR_QB_PH_MMR2 : DspMMRel, PRECR_QB_PH_MMR2_ENC, PRECR_QB_PH_DESC, 588 ISA_DSPR2; 589 def PRECR_SRA_PH_W_MMR2 : DspMMRel, PRECR_SRA_PH_W_MMR2_ENC, 590 PRECR_SRA_PH_W_DESC, ISA_DSPR2; 591 def PRECR_SRA_R_PH_W_MMR2 : DspMMRel, PRECR_SRA_R_PH_W_MMR2_ENC, 592 PRECR_SRA_R_PH_W_DESC, ISA_DSPR2; 593 def PREPEND_MMR2 : DspMMRel, PREPEND_MMR2_ENC, PREPEND_DESC, ISA_DSPR2; 594 595 // Instruction alias. 596 def : MMDSPInstAlias<"wrdsp $rt", (WRDSP_MM GPR32Opnd:$rt, 0x1F), 1>; 597 def APPEND_MMR2 : DspMMRel, APPEND_MMR2_ENC, APPEND_DESC, ISA_DSPR2; 598 def MULSA_W_PH_MMR2 : DspMMRel, MULSA_W_PH_MMR2_ENC, MULSA_W_PH_DESC, ISA_DSPR2; 599 // microMIPS DSP Rev 3 600 def BPOSGE32C_MMR3 : DspMMRel, BPOSGE32C_MMR3_ENC, BPOSGE32C_MMR3_DESC, 601 ISA_DSPR3; 602
