1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips64 instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Mips Operand, Complex Patterns and Transformations Definitions. 16 //===----------------------------------------------------------------------===// 17 18 // Transformation Function - get Imm - 32. 19 def Subtract32 : SDNodeXForm<imm, [{ 20 return getImm(N, (unsigned)N->getZExtValue() - 32); 21 }]>; 22 23 // shamt must fit in 6 bits. 24 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 25 26 // Node immediate fits as 10-bit sign extended on target immediate. 27 // e.g. seqi, snei 28 def immSExt10_64 : PatLeaf<(i64 imm), 29 [{ return isInt<10>(N->getSExtValue()); }]>; 30 31 def immZExt16_64 : PatLeaf<(i64 imm), 32 [{ return isUInt<16>(N->getZExtValue()); }]>; 33 34 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>; 35 36 // Transformation function: get log2 of low 32 bits of immediate 37 def Log2LO : SDNodeXForm<imm, [{ 38 return getImm(N, Log2_64((unsigned) N->getZExtValue())); 39 }]>; 40 41 // Transformation function: get log2 of high 32 bits of immediate 42 def Log2HI : SDNodeXForm<imm, [{ 43 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32))); 44 }]>; 45 46 // Predicate: True if immediate is a power of 2 and fits 32 bits 47 def PowerOf2LO : PatLeaf<(imm), [{ 48 if (N->getValueType(0) == MVT::i64) { 49 uint64_t Imm = N->getZExtValue(); 50 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm; 51 } 52 else 53 return false; 54 }]>; 55 56 // Predicate: True if immediate is a power of 2 and exceeds 32 bits 57 def PowerOf2HI : PatLeaf<(imm), [{ 58 if (N->getValueType(0) == MVT::i64) { 59 uint64_t Imm = N->getZExtValue(); 60 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; 61 } 62 else 63 return false; 64 }]>; 65 66 def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ 67 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32); 68 }]>; 69 70 //===----------------------------------------------------------------------===// 71 // Instructions specific format 72 //===----------------------------------------------------------------------===// 73 let usesCustomInserter = 1 in { 74 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 75 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 76 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 77 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 78 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 79 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 80 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 81 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 82 } 83 84 /// Pseudo instructions for loading and storing accumulator registers. 85 let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in { 86 def LOAD_ACC128 : Load<"", ACC128>; 87 def STORE_ACC128 : Store<"", ACC128>; 88 } 89 90 //===----------------------------------------------------------------------===// 91 // Instruction definition 92 //===----------------------------------------------------------------------===// 93 let DecoderNamespace = "Mips64" in { 94 /// Arithmetic Instructions (ALU Immediate) 95 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>, 96 ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6; 97 let AdditionalPredicates = [NotInMicroMips] in { 98 def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd, 99 II_DADDIU, immSExt16, add>, 100 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; 101 } 102 103 let isCodeGenOnly = 1 in { 104 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 105 SLTI_FM<0xa>; 106 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 107 SLTI_FM<0xb>; 108 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>, 109 ADDI_FM<0xc>; 110 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>, 111 ADDI_FM<0xd>; 112 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, 113 ADDI_FM<0xe>; 114 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM; 115 } 116 117 /// Arithmetic Instructions (3-Operand, R-Type) 118 let AdditionalPredicates = [NotInMicroMips] in { 119 def DADD : StdMMR6Rel, ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, 120 ADD_FM<0, 0x2c>, ISA_MIPS3; 121 def DADDu : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, 122 ADD_FM<0, 0x2d>, ISA_MIPS3; 123 def DSUBu : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>, 124 ISA_MIPS3; 125 def DSUB : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, 126 ISA_MIPS3; 127 } 128 129 let isCodeGenOnly = 1 in { 130 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 131 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>; 132 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; 133 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>; 134 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; 135 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>; 136 } 137 138 /// Shift Instructions 139 let AdditionalPredicates = [NotInMicroMips] in { 140 def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, 141 shl, immZExt6>, 142 SRA_FM<0x38, 0>, ISA_MIPS3; 143 def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, 144 srl, immZExt6>, 145 SRA_FM<0x3a, 0>, ISA_MIPS3; 146 def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, 147 sra, immZExt6>, 148 SRA_FM<0x3b, 0>, ISA_MIPS3; 149 def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, 150 SRLV_FM<0x14, 0>, ISA_MIPS3; 151 def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, 152 SRLV_FM<0x17, 0>, ISA_MIPS3; 153 def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, 154 SRLV_FM<0x16, 0>, ISA_MIPS3; 155 def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, 156 II_DSLL32>, 157 SRA_FM<0x3c, 0>, ISA_MIPS3; 158 def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, 159 II_DSRL32>, 160 SRA_FM<0x3e, 0>, ISA_MIPS3; 161 def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, 162 II_DSRA32>, 163 SRA_FM<0x3f, 0>, ISA_MIPS3; 164 165 // Rotate Instructions 166 def DROTR : StdMMR6Rel, shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, 167 rotr, immZExt6>, 168 SRA_FM<0x3a, 1>, ISA_MIPS64R2; 169 def DROTRV : StdMMR6Rel, shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, 170 rotr>, 171 SRLV_FM<0x16, 1>, ISA_MIPS64R2; 172 def DROTR32 : StdMMR6Rel, shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, 173 II_DROTR32>, 174 SRA_FM<0x3e, 1>, ISA_MIPS64R2; 175 } 176 177 /// Load and Store Instructions 178 /// aligned 179 let isCodeGenOnly = 1 in { 180 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>; 181 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>; 182 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>; 183 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>; 184 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>; 185 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>; 186 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>; 187 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>; 188 } 189 190 let AdditionalPredicates = [NotInMicroMips] in { 191 def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, 192 LW_FM<0x27>, ISA_MIPS3; 193 def LD : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>, 194 LW_FM<0x37>, ISA_MIPS3; 195 def SD : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>, 196 LW_FM<0x3f>, ISA_MIPS3; 197 } 198 199 200 201 /// load/store left/right 202 let isCodeGenOnly = 1 in { 203 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>; 204 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>; 205 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>; 206 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>; 207 } 208 209 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>, 210 ISA_MIPS3_NOT_32R6_64R6; 211 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>, 212 ISA_MIPS3_NOT_32R6_64R6; 213 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>, 214 ISA_MIPS3_NOT_32R6_64R6; 215 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>, 216 ISA_MIPS3_NOT_32R6_64R6; 217 218 /// Load-linked, Store-conditional 219 let AdditionalPredicates = [NotInMicroMips] in { 220 def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>, 221 ISA_MIPS3_NOT_32R6_64R6; 222 } 223 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; 224 225 let AdditionalPredicates = [NotInMicroMips], 226 DecoderNamespace = "Mips32_64_PTR64" in { 227 def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64, 228 ISA_MIPS2_NOT_32R6_64R6; 229 def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64, 230 ISA_MIPS2_NOT_32R6_64R6; 231 } 232 233 /// Jump and Branch Instructions 234 let isCodeGenOnly = 1 in { 235 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>; 236 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>; 237 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>; 238 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>; 239 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; 240 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; 241 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 242 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; 243 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; 244 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>; 245 } 246 247 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; 248 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>; 249 250 /// Multiply and Divide Instructions. 251 let AdditionalPredicates = [NotInMicroMips] in { 252 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, 253 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6; 254 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, 255 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6; 256 } 257 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 258 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6; 259 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 260 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6; 261 let AdditionalPredicates = [NotInMicroMips] in { 262 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, 263 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6; 264 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, 265 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6; 266 } 267 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 268 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 269 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 270 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 271 272 let isCodeGenOnly = 1 in { 273 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>, 274 ISA_MIPS3_NOT_32R6_64R6; 275 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>, 276 ISA_MIPS3_NOT_32R6_64R6; 277 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>, 278 ISA_MIPS3_NOT_32R6_64R6; 279 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>, 280 ISA_MIPS3_NOT_32R6_64R6; 281 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>, 282 ISA_MIPS3_NOT_32R6_64R6; 283 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>, 284 ISA_MIPS3_NOT_32R6_64R6; 285 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6; 286 287 /// Sign Ext In Register Instructions. 288 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>, 289 ISA_MIPS32R2; 290 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, 291 ISA_MIPS32R2; 292 } 293 294 /// Count Leading 295 let AdditionalPredicates = [NotInMicroMips] in { 296 def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, 297 ISA_MIPS64_NOT_64R6; 298 def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, 299 ISA_MIPS64_NOT_64R6; 300 301 /// Double Word Swap Bytes/HalfWords 302 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2; 303 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2; 304 } 305 306 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; 307 308 let isCodeGenOnly = 1 in 309 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; 310 311 let AdditionalPredicates = [NotInMicroMips] in { 312 // The 'pos + size' constraints are enforced by the code that lowers into 313 // MipsISD::Ext. 314 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1, 315 immZExt5, immZExt5Plus1, MipsExt>, EXT_FM<3>, 316 ISA_MIPS64R2; 317 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5, 318 immZExt5Plus33, MipsExt>, EXT_FM<1>, ISA_MIPS64R2; 319 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, 320 immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>, 321 ISA_MIPS64R2; 322 def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, MipsIns>, 323 EXT_FM<7>, ISA_MIPS64R2; 324 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1>, 325 EXT_FM<6>, ISA_MIPS64R2; 326 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm5_inssize_plus1>, 327 EXT_FM<5>, ISA_MIPS64R2; 328 } 329 330 let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 331 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 332 "dsll\t$rd, $rt, 32", [], II_DSLL>; 333 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 334 "sll\t$rd, $rt, 0", [], II_SLL>; 335 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 336 "sll\t$rd, $rt, 0", [], II_SLL>; 337 } 338 339 // We need the following pseudo instruction to avoid offset calculation for 340 // long branches. See the comment in file MipsLongBranch.cpp for detailed 341 // explanation. 342 343 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt) 344 // where %PART may be %hi or %lo, depending on the relocation kind 345 // that $tgt is annotated with. 346 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst), 347 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>; 348 349 // Cavium Octeon cnMIPS instructions 350 let DecoderNamespace = "CnMips", 351 // FIXME: The lack of HasStdEnc is probably a bug 352 EncodingPredicates = []<Predicate> in { 353 354 class Count1s<string opstr, RegisterOperand RO>: 355 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 356 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { 357 let TwoOperandAliasConstraint = "$rd = $rs"; 358 } 359 360 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>: 361 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1), 362 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"), 363 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))], 364 NoItinerary, FrmR, opstr> { 365 let TwoOperandAliasConstraint = "$rt = $rs"; 366 } 367 368 class SetCC64_R<string opstr, PatFrag cond_op> : 369 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 370 !strconcat(opstr, "\t$rd, $rs, $rt"), 371 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs, 372 GPR64Opnd:$rt)))], 373 II_SEQ_SNE, FrmR, opstr> { 374 let TwoOperandAliasConstraint = "$rd = $rs"; 375 } 376 377 class SetCC64_I<string opstr, PatFrag cond_op>: 378 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10), 379 !strconcat(opstr, "\t$rt, $rs, $imm10"), 380 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs, 381 immSExt10_64:$imm10)))], 382 II_SEQI_SNEI, FrmI, opstr> { 383 let TwoOperandAliasConstraint = "$rt = $rs"; 384 } 385 386 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, 387 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> : 388 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset), 389 !strconcat(opstr, "\t$rs, $p, $offset"), 390 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), 391 bb:$offset)], II_BBIT, FrmI, opstr> { 392 let isBranch = 1; 393 let isTerminator = 1; 394 let hasDelaySlot = 1; 395 let Defs = [AT]; 396 } 397 398 class MFC2OP<string asmstr, RegisterOperand RO> : 399 InstSE<(outs RO:$rt, uimm16:$imm16), (ins), 400 !strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>; 401 402 // Unsigned Byte Add 403 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, 404 ADD_FM<0x1c, 0x28>, ASE_CNMIPS { 405 let Pattern = [(set GPR64Opnd:$rd, 406 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))]; 407 } 408 409 // Branch on Bit Clear /+32 410 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, 411 uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS; 412 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64, 413 0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS; 414 415 // Branch on Bit Set /+32 416 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, 417 uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS; 418 def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, 419 0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS; 420 421 // Multiply Doubleword to GPR 422 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, 423 ADD_FM<0x1c, 0x03>, ASE_CNMIPS { 424 let Defs = [HI0, LO0, P0, P1, P2]; 425 } 426 427 // Extract a signed bit field /+32 428 def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>, ASE_CNMIPS; 429 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>, ASE_CNMIPS; 430 431 // Clear and insert a bit field /+32 432 def CINS : ExtsCins<"cins">, EXTS_FM<0x32>, ASE_CNMIPS; 433 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>, ASE_CNMIPS; 434 435 // Move to multiplier/product register 436 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>, 437 ASE_CNMIPS; 438 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>, 439 ASE_CNMIPS; 440 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>, 441 ASE_CNMIPS; 442 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>, ASE_CNMIPS; 443 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>, ASE_CNMIPS; 444 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>, ASE_CNMIPS; 445 446 // Count Ones in a Word/Doubleword 447 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>, ASE_CNMIPS; 448 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>, ASE_CNMIPS; 449 450 // Set on equal/not equal 451 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>, ASE_CNMIPS; 452 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>, ASE_CNMIPS; 453 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS; 454 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS; 455 456 // 192-bit x 64-bit Unsigned Multiply and Add 457 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>, 458 ASE_CNMIPS { 459 let Defs = [P0, P1, P2]; 460 } 461 462 // 64-bit Unsigned Multiply and Add Move 463 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>, 464 ASE_CNMIPS { 465 let Defs = [MPL0, P0, P1, P2]; 466 } 467 468 // 64-bit Unsigned Multiply and Add 469 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>, 470 ASE_CNMIPS { 471 let Defs = [MPL1, MPL2, P0, P1, P2]; 472 } 473 474 // Move between CPU and coprocessor registers 475 def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>, ASE_CNMIPS; 476 def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>, ASE_CNMIPS; 477 } 478 479 } 480 481 /// Move between CPU and coprocessor registers 482 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { 483 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd, II_DMFC0>, MFC3OP_FM<0x10, 1>, 484 ISA_MIPS3; 485 def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>, MFC3OP_FM<0x10, 5>, 486 ISA_MIPS3; 487 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd, II_DMFC2>, MFC3OP_FM<0x12, 1>, 488 ISA_MIPS3; 489 def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, MFC3OP_FM<0x12, 5>, 490 ISA_MIPS3; 491 } 492 493 //===----------------------------------------------------------------------===// 494 // Arbitrary patterns that map to one or more instructions 495 //===----------------------------------------------------------------------===// 496 497 // extended loads 498 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 499 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 500 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 501 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 502 503 // hi/lo relocs 504 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 505 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 506 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 507 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 508 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 509 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 510 511 let AdditionalPredicates = [NotInMicroMips] in { 512 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 513 def : MipsPat<(MipsLo tblockaddress:$in), 514 (DADDiu ZERO_64, tblockaddress:$in)>; 515 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 516 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 517 def : MipsPat<(MipsLo tglobaltlsaddr:$in), 518 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 519 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 520 521 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)), 522 (DADDiu GPR64:$hi, tglobaladdr:$lo)>; 523 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)), 524 (DADDiu GPR64:$hi, tblockaddress:$lo)>; 525 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)), 526 (DADDiu GPR64:$hi, tjumptable:$lo)>; 527 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)), 528 (DADDiu GPR64:$hi, tconstpool:$lo)>; 529 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)), 530 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>; 531 532 def : WrapperPat<tglobaladdr, DADDiu, GPR64>; 533 def : WrapperPat<tconstpool, DADDiu, GPR64>; 534 def : WrapperPat<texternalsym, DADDiu, GPR64>; 535 def : WrapperPat<tblockaddress, DADDiu, GPR64>; 536 def : WrapperPat<tjumptable, DADDiu, GPR64>; 537 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; 538 } 539 540 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 541 ZERO_64>; 542 543 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 544 (BLEZ64 i64:$lhs, bb:$dst)>; 545 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 546 (BGEZ64 i64:$lhs, bb:$dst)>; 547 548 // setcc patterns 549 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; 550 defm : SetlePats<GPR64, SLT64, SLTu64>; 551 defm : SetgtPats<GPR64, SLT64, SLTu64>; 552 defm : SetgePats<GPR64, SLT64, SLTu64>; 553 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; 554 555 // truncate 556 def : MipsPat<(trunc (assertsext GPR64:$src)), 557 (EXTRACT_SUBREG GPR64:$src, sub_32)>; 558 // The forward compatibility strategy employed by MIPS requires us to treat 559 // values as being sign extended to an infinite number of bits. This allows 560 // existing software to run without modification on any future MIPS 561 // implementation (e.g. 128-bit, or 1024-bit). Being compatible with this 562 // strategy requires that truncation acts as a sign-extension for values being 563 // fed into instructions operating on 32-bit values. Such instructions have 564 // undefined results if this is not true. 565 // For our case, this means that we can't issue an extract_subreg for nodes 566 // such as (trunc:i32 (assertzext:i64 X, i32)), because the sign-bit of the 567 // lower subreg would not be replicated into the upper half. 568 def : MipsPat<(trunc (assertzext_lt_i32 GPR64:$src)), 569 (EXTRACT_SUBREG GPR64:$src, sub_32)>; 570 def : MipsPat<(i32 (trunc GPR64:$src)), 571 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; 572 573 // variable shift instructions patterns 574 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))), 575 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 576 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))), 577 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 578 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))), 579 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 580 let AdditionalPredicates = [NotInMicroMips] in { 581 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), 582 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 583 } 584 585 // 32-to-64-bit extension 586 def : MipsPat<(i64 (anyext GPR32:$src)), 587 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; 588 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; 589 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; 590 591 // Sign extend in register 592 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 593 (SLL64_64 GPR64:$src)>; 594 595 // bswap MipsPattern 596 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; 597 598 // Carry pattern 599 let AdditionalPredicates = [NotInMicroMips] in { 600 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), 601 (DSUBu GPR64:$lhs, GPR64:$rhs)>; 602 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), 603 (DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP; 604 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), 605 (DADDiu GPR64:$lhs, imm:$imm)>, ASE_NOT_DSP; 606 } 607 608 // Octeon bbit0/bbit1 MipsPattern 609 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 610 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; 611 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 612 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; 613 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 614 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; 615 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 616 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; 617 618 // Atomic load patterns. 619 def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>; 620 def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>; 621 def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>; 622 def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>; 623 624 // Atomic store patterns. 625 def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>; 626 def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>; 627 def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>; 628 def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>; 629 630 //===----------------------------------------------------------------------===// 631 // Instruction aliases 632 //===----------------------------------------------------------------------===// 633 let AdditionalPredicates = [NotInMicroMips] in { 634 def : MipsInstAlias<"move $dst, $src", 635 (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 636 GPR_64; 637 def : MipsInstAlias<"move $dst, $src", 638 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 639 GPR_64; 640 def : MipsInstAlias<"dadd $rs, $rt, $imm", 641 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 642 0>, ISA_MIPS3_NOT_32R6_64R6; 643 def : MipsInstAlias<"dadd $rs, $imm", 644 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 645 0>, ISA_MIPS3_NOT_32R6_64R6; 646 def : MipsInstAlias<"daddu $rs, $rt, $imm", 647 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 648 0>, ISA_MIPS3; 649 def : MipsInstAlias<"daddu $rs, $imm", 650 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 651 0>, ISA_MIPS3; 652 } 653 def : MipsInstAlias<"dsll $rd, $rt, $rs", 654 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 655 ISA_MIPS3; 656 let AdditionalPredicates = [NotInMicroMips] in { 657 def : MipsInstAlias<"dneg $rt, $rs", 658 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 659 ISA_MIPS3; 660 def : MipsInstAlias<"dneg $rt", 661 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>, 662 ISA_MIPS3; 663 def : MipsInstAlias<"dnegu $rt, $rs", 664 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 665 ISA_MIPS3; 666 } 667 def : MipsInstAlias<"dsubi $rs, $rt, $imm", 668 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 669 InvertedImOperand64:$imm), 670 0>, ISA_MIPS3_NOT_32R6_64R6; 671 def : MipsInstAlias<"dsubi $rs, $imm", 672 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 673 InvertedImOperand64:$imm), 674 0>, ISA_MIPS3_NOT_32R6_64R6; 675 def : MipsInstAlias<"dsub $rs, $rt, $imm", 676 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 677 InvertedImOperand64:$imm), 678 0>, ISA_MIPS3_NOT_32R6_64R6; 679 def : MipsInstAlias<"dsub $rs, $imm", 680 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 681 InvertedImOperand64:$imm), 682 0>, ISA_MIPS3_NOT_32R6_64R6; 683 let AdditionalPredicates = [NotInMicroMips] in { 684 def : MipsInstAlias<"dsubu $rt, $rs, $imm", 685 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, 686 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 687 def : MipsInstAlias<"dsubu $rs, $imm", 688 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, 689 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 690 } 691 def : MipsInstAlias<"dsra $rd, $rt, $rs", 692 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 693 ISA_MIPS3; 694 let AdditionalPredicates = [NotInMicroMips] in { 695 def : MipsInstAlias<"dsrl $rd, $rt, $rs", 696 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 697 ISA_MIPS3; 698 699 // Two operand (implicit 0 selector) versions: 700 def : MipsInstAlias<"dmtc0 $rt, $rd", 701 (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 702 def : MipsInstAlias<"dmfc0 $rt, $rd", 703 (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; 704 } 705 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; 706 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 707 708 def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS; 709 def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS; 710 def : MipsInstAlias<"syncw", (SYNC 0x4), 0>, ASE_MIPS64_CNMIPS; 711 def : MipsInstAlias<"syncws", (SYNC 0x5), 0>, ASE_MIPS64_CNMIPS; 712 713 // cnMIPS Aliases. 714 715 // bbit* with $p 32-63 converted to bbit*32 with $p 0-31 716 def : MipsInstAlias<"bbit0 $rs, $p, $offset", 717 (BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 718 brtarget:$offset), 0>, 719 ASE_CNMIPS; 720 def : MipsInstAlias<"bbit1 $rs, $p, $offset", 721 (BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 722 brtarget:$offset), 0>, 723 ASE_CNMIPS; 724 725 // exts with $pos 32-63 in converted to exts32 with $pos 0-31 726 def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1", 727 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 728 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 729 ASE_CNMIPS; 730 def : MipsInstAlias<"exts $rt, $pos, $lenm1", 731 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 732 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 733 ASE_CNMIPS; 734 735 // cins with $pos 32-63 in converted to cins32 with $pos 0-31 736 def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1", 737 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 738 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 739 ASE_CNMIPS; 740 def : MipsInstAlias<"cins $rt, $pos, $lenm1", 741 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 742 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 743 ASE_CNMIPS; 744 745 //===----------------------------------------------------------------------===// 746 // Assembler Pseudo Instructions 747 //===----------------------------------------------------------------------===// 748 749 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> : 750 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64), 751 !strconcat(instr_asm, "\t$rt, $imm64")> ; 752 def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>; 753 754 def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr), 755 "dla\t$rt, $addr">; 756 def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64), 757 "dla\t$rt, $imm64">; 758
