1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips MSA ASE instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 16 SDTCisInt<1>, 17 SDTCisSameAs<1, 2>, 18 SDTCisVT<3, OtherVT>]>; 19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 20 SDTCisFP<1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisVT<3, OtherVT>]>; 23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 24 SDTCisInt<1>, SDTCisVec<1>, 25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 30 def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 32 SDTCisVT<4, i32>]>; 33 34 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 35 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 36 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 37 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 38 def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp, 39 [SDNPCommutative, SDNPAssociative]>; 40 def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp, 41 [SDNPCommutative, SDNPAssociative]>; 42 def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp, 43 [SDNPCommutative, SDNPAssociative]>; 44 def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 49 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 50 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 51 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 52 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 53 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 54 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 55 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 56 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 57 58 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 59 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 60 61 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 62 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 63 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 64 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 65 66 def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 67 def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 68 def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 69 def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 70 71 // Operands 72 73 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 74 75 // Pattern fragments 76 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 77 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 78 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 79 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 80 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 81 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 82 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 83 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 84 85 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 86 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 87 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 88 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 89 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 90 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 91 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 92 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 93 94 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 95 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 96 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 97 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 98 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 99 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 100 def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 101 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 102 103 def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 104 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 105 def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 106 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 107 def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 108 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 109 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 110 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 111 112 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 113 PatFrag<(ops node:$lhs, node:$rhs), 114 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 115 116 // ISD::SETFALSE cannot occur 117 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 118 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 119 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 120 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 121 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 122 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 123 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 124 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 125 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 126 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 127 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 128 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 129 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 130 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 131 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 132 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 133 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 134 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 135 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 136 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 137 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 138 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 139 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 140 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 141 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 142 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 143 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 144 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 145 // ISD::SETTRUE cannot occur 146 // ISD::SETFALSE2 cannot occur 147 // ISD::SETTRUE2 cannot occur 148 149 class vsetcc_type<ValueType ResTy, CondCode CC> : 150 PatFrag<(ops node:$lhs, node:$rhs), 151 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 152 153 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 154 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 155 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 156 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 157 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 158 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 159 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 160 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 161 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 162 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 163 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 164 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 165 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 166 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 167 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 168 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 169 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 170 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 171 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 172 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 173 174 def vsplati8 : PatFrag<(ops node:$e0), 175 (v16i8 (build_vector node:$e0, node:$e0, 176 node:$e0, node:$e0, 177 node:$e0, node:$e0, 178 node:$e0, node:$e0, 179 node:$e0, node:$e0, 180 node:$e0, node:$e0, 181 node:$e0, node:$e0, 182 node:$e0, node:$e0))>; 183 def vsplati16 : PatFrag<(ops node:$e0), 184 (v8i16 (build_vector node:$e0, node:$e0, 185 node:$e0, node:$e0, 186 node:$e0, node:$e0, 187 node:$e0, node:$e0))>; 188 def vsplati32 : PatFrag<(ops node:$e0), 189 (v4i32 (build_vector node:$e0, node:$e0, 190 node:$e0, node:$e0))>; 191 def vsplati64 : PatFrag<(ops node:$e0), 192 (v2i64 (build_vector node:$e0, node:$e0))>; 193 def vsplatf32 : PatFrag<(ops node:$e0), 194 (v4f32 (build_vector node:$e0, node:$e0, 195 node:$e0, node:$e0))>; 196 def vsplatf64 : PatFrag<(ops node:$e0), 197 (v2f64 (build_vector node:$e0, node:$e0))>; 198 199 def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 200 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 201 def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 202 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 203 def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 204 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 205 def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 206 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>; 207 208 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 209 SDNodeXForm xform = NOOP_SDNodeXForm> 210 : PatLeaf<frag, pred, xform> { 211 Operand OpClass = opclass; 212 } 213 214 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 215 list<SDNode> roots = [], 216 list<SDNodeProperty> props = []> : 217 ComplexPattern<ty, numops, fn, roots, props> { 218 Operand OpClass = opclass; 219 } 220 221 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 222 "selectVSplatUimm3", 223 [build_vector, bitconvert]>; 224 225 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 226 "selectVSplatUimm4", 227 [build_vector, bitconvert]>; 228 229 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 230 "selectVSplatUimm5", 231 [build_vector, bitconvert]>; 232 233 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 234 "selectVSplatUimm8", 235 [build_vector, bitconvert]>; 236 237 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 238 "selectVSplatSimm5", 239 [build_vector, bitconvert]>; 240 241 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 242 "selectVSplatUimm3", 243 [build_vector, bitconvert]>; 244 245 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 246 "selectVSplatUimm4", 247 [build_vector, bitconvert]>; 248 249 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 250 "selectVSplatUimm5", 251 [build_vector, bitconvert]>; 252 253 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 254 "selectVSplatSimm5", 255 [build_vector, bitconvert]>; 256 257 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 258 "selectVSplatUimm2", 259 [build_vector, bitconvert]>; 260 261 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 262 "selectVSplatUimm5", 263 [build_vector, bitconvert]>; 264 265 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 266 "selectVSplatSimm5", 267 [build_vector, bitconvert]>; 268 269 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 270 "selectVSplatUimm1", 271 [build_vector, bitconvert]>; 272 273 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 274 "selectVSplatUimm5", 275 [build_vector, bitconvert]>; 276 277 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 278 "selectVSplatUimm6", 279 [build_vector, bitconvert]>; 280 281 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 282 "selectVSplatSimm5", 283 [build_vector, bitconvert]>; 284 285 // Any build_vector that is a constant splat with a value that is an exact 286 // power of 2 287 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 288 [build_vector, bitconvert]>; 289 290 // Any build_vector that is a constant splat with a value that is the bitwise 291 // inverse of an exact power of 2 292 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 293 [build_vector, bitconvert]>; 294 295 // Any build_vector that is a constant splat with only a consecutive sequence 296 // of left-most bits set. 297 def vsplat_maskl_bits_uimm3 298 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", 299 [build_vector, bitconvert]>; 300 def vsplat_maskl_bits_uimm4 301 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", 302 [build_vector, bitconvert]>; 303 def vsplat_maskl_bits_uimm5 304 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", 305 [build_vector, bitconvert]>; 306 def vsplat_maskl_bits_uimm6 307 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", 308 [build_vector, bitconvert]>; 309 310 // Any build_vector that is a constant splat with only a consecutive sequence 311 // of right-most bits set. 312 def vsplat_maskr_bits_uimm3 313 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", 314 [build_vector, bitconvert]>; 315 def vsplat_maskr_bits_uimm4 316 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", 317 [build_vector, bitconvert]>; 318 def vsplat_maskr_bits_uimm5 319 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", 320 [build_vector, bitconvert]>; 321 def vsplat_maskr_bits_uimm6 322 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", 323 [build_vector, bitconvert]>; 324 325 // Any build_vector that is a constant splat with a value that equals 1 326 // FIXME: These should be a ComplexPattern but we can't use them because the 327 // ISel generator requires the uses to have a name, but providing a name 328 // causes other errors ("used in pattern but not operand list") 329 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 330 APInt Imm; 331 EVT EltTy = N->getValueType(0).getVectorElementType(); 332 333 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 334 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 335 }]>; 336 337 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 338 APInt Imm; 339 SDNode *BV = N->getOperand(0).getNode(); 340 EVT EltTy = N->getValueType(0).getVectorElementType(); 341 342 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 343 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 344 }]>; 345 346 def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 347 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 348 immAllOnesV))>; 349 def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 350 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 351 immAllOnesV))>; 352 def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 353 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 354 immAllOnesV))>; 355 def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 356 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 357 node:$wt), 358 (bitconvert (v4i32 immAllOnesV))))>; 359 360 def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 361 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 362 def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 363 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 364 def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 365 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 366 def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 367 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 368 node:$wt))>; 369 370 def vbset_b : PatFrag<(ops node:$ws, node:$wt), 371 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 372 def vbset_h : PatFrag<(ops node:$ws, node:$wt), 373 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 374 def vbset_w : PatFrag<(ops node:$ws, node:$wt), 375 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 376 def vbset_d : PatFrag<(ops node:$ws, node:$wt), 377 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 378 node:$wt))>; 379 380 def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt), 381 (fsub node:$wd, (fmul node:$ws, node:$wt))>; 382 383 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 384 (add node:$wd, (mul node:$ws, node:$wt))>; 385 386 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 387 (sub node:$wd, (mul node:$ws, node:$wt))>; 388 389 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 390 (fmul node:$ws, (fexp2 node:$wt))>; 391 392 // Immediates 393 def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>; 394 def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>; 395 396 // Instruction encoding. 397 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 398 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 399 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 400 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 401 402 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 403 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 404 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 405 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 406 407 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 408 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 409 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 410 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 411 412 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 413 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 414 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 415 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 416 417 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 418 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 419 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 420 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 421 422 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 423 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 424 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 425 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 426 427 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 428 429 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 430 431 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 432 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 433 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 434 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 435 436 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 437 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 438 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 439 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 440 441 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 442 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 443 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 444 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 445 446 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 447 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 448 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 449 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 450 451 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 452 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 453 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 454 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 455 456 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 457 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 458 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 459 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 460 461 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 462 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 463 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 464 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 465 466 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 467 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 468 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 469 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 470 471 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 472 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 473 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 474 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 475 476 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 477 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 478 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 479 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 480 481 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 482 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 483 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 484 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 485 486 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 487 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 488 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 489 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 490 491 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 492 493 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 494 495 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 496 497 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 498 499 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 500 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 501 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 502 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 503 504 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 505 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 506 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 507 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 508 509 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 510 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 511 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 512 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 513 514 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 515 516 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 517 518 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 519 520 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 521 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 522 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 523 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 524 525 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 526 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 527 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 528 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 529 530 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 531 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 532 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 533 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 534 535 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 536 537 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 538 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 539 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 540 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 541 542 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 543 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 544 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 545 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 546 547 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 548 549 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 550 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 551 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 552 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 553 554 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 555 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 556 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 557 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 558 559 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 560 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 561 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 562 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 563 564 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 565 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 566 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 567 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 568 569 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 570 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 571 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 572 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 573 574 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 575 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 576 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 577 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 578 579 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 580 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 581 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 582 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 583 584 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 585 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 586 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 587 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 588 589 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 590 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 591 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 592 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 593 594 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 595 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 596 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 597 598 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 599 600 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 601 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 602 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 603 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 604 605 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 606 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 607 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 608 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 609 610 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 611 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 612 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 613 614 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 615 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 616 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 617 618 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 619 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 620 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 621 622 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 623 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 624 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 625 626 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 627 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 628 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 629 630 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 631 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 632 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 633 634 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 635 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 636 637 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 638 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 639 640 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 641 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 642 643 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 644 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 645 646 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 647 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 648 649 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 650 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 651 652 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 653 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 654 655 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 656 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 657 658 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 659 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 660 661 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 662 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 663 664 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 665 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 666 667 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 668 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 669 670 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 671 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 672 673 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 674 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 675 676 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 677 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 678 679 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 680 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 681 682 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 683 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 684 685 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 686 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 687 688 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 689 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 690 691 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 692 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 693 694 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 695 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 696 697 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 698 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 699 700 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 701 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 702 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 703 class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 704 705 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 706 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 707 708 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 709 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 710 711 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 712 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 713 714 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 715 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 716 717 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 718 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 719 720 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 721 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 722 723 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 724 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 725 726 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 727 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 728 729 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 730 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 731 732 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 733 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 734 735 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 736 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 737 738 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 739 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 740 741 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 742 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 743 744 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 745 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 746 747 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 748 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 749 750 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 751 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 752 753 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 754 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 755 756 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 757 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 758 759 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 760 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 761 762 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 763 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 764 765 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 766 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 767 768 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 769 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 770 771 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 772 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 773 774 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 775 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 776 777 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 778 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 779 780 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 781 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 782 783 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 784 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 785 786 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 787 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 788 789 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 790 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 791 792 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 793 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 794 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 795 796 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 797 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 798 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 799 800 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 801 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 802 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 803 804 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 805 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 806 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 807 808 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 809 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 810 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 811 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 812 813 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 814 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 815 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 816 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 817 818 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 819 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 820 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 821 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 822 823 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 824 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 825 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 826 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 827 828 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 829 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 830 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 831 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 832 833 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 834 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 835 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 836 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 837 838 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 839 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 840 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 841 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 842 843 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 844 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 845 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 846 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 847 848 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 849 class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 850 851 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 852 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 853 854 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 855 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 856 857 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 858 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 859 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 860 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 861 862 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 863 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 864 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 865 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 866 867 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 868 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 869 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 870 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 871 872 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 873 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 874 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 875 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 876 877 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 878 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 879 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 880 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 881 882 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 883 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 884 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 885 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 886 887 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 888 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 889 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 890 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 891 892 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 893 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 894 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 895 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 896 897 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 898 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 899 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 900 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 901 902 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 903 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 904 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 905 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 906 907 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 908 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 909 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 910 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 911 912 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 913 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 914 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 915 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 916 917 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 918 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 919 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 920 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 921 922 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 923 924 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 925 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 926 927 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 928 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 929 930 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 931 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 932 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 933 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 934 935 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 936 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 937 938 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 939 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 940 941 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 942 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 943 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 944 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 945 946 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 947 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 948 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 949 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 950 951 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 952 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 953 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 954 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 955 956 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 957 958 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 959 960 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 961 962 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 963 964 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 965 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 966 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 967 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 968 969 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 970 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 971 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 972 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 973 974 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 975 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 976 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 977 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 978 979 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 980 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 981 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 982 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 983 984 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 985 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 986 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 987 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 988 989 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 990 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 991 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 992 993 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 994 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 995 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 996 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 997 998 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 999 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 1000 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 1001 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1002 1003 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1004 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1005 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1006 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1007 1008 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1009 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1010 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1011 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1012 1013 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1014 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1015 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1016 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1017 1018 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1019 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1020 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1021 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1022 1023 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1024 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1025 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1026 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1027 1028 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1029 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1030 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1031 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1032 1033 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1034 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1035 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1036 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1037 1038 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1039 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1040 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1041 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1042 1043 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1044 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1045 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1046 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1047 1048 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1049 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1050 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1051 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1052 1053 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1054 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1055 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1056 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1057 1058 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1059 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1060 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1061 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1062 1063 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1064 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1065 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1066 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1067 1068 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1069 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1070 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1071 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1072 1073 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1074 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1075 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1076 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1077 1078 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1079 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1080 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1081 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1082 1083 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1084 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1085 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1086 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1087 1088 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1089 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1090 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1091 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1092 1093 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1094 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1095 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1096 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1097 1098 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1099 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1100 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1101 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1102 1103 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1104 1105 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1106 1107 // Instruction desc. 1108 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1109 ComplexPattern Imm, RegisterOperand ROWD, 1110 RegisterOperand ROWS = ROWD, 1111 InstrItinClass itin = NoItinerary> { 1112 dag OutOperandList = (outs ROWD:$wd); 1113 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1114 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1115 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1116 InstrItinClass Itinerary = itin; 1117 } 1118 1119 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1120 ComplexPattern Imm, RegisterOperand ROWD, 1121 RegisterOperand ROWS = ROWD, 1122 InstrItinClass itin = NoItinerary> { 1123 dag OutOperandList = (outs ROWD:$wd); 1124 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1125 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1126 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1127 InstrItinClass Itinerary = itin; 1128 } 1129 1130 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1131 ComplexPattern Imm, RegisterOperand ROWD, 1132 RegisterOperand ROWS = ROWD, 1133 InstrItinClass itin = NoItinerary> { 1134 dag OutOperandList = (outs ROWD:$wd); 1135 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1136 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1137 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1138 InstrItinClass Itinerary = itin; 1139 } 1140 1141 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1142 ComplexPattern Imm, RegisterOperand ROWD, 1143 RegisterOperand ROWS = ROWD, 1144 InstrItinClass itin = NoItinerary> { 1145 dag OutOperandList = (outs ROWD:$wd); 1146 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1147 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1148 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1149 InstrItinClass Itinerary = itin; 1150 } 1151 1152 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1153 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1154 RegisterOperand ROWS = ROWD, 1155 InstrItinClass itin = NoItinerary> { 1156 dag OutOperandList = (outs ROWD:$wd); 1157 dag InOperandList = (ins ROWS:$ws, ImmOp:$m); 1158 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1159 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1160 InstrItinClass Itinerary = itin; 1161 } 1162 1163 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1164 SplatComplexPattern Mask, RegisterOperand ROWD, 1165 RegisterOperand ROWS = ROWD, 1166 InstrItinClass itin = NoItinerary> { 1167 dag OutOperandList = (outs ROWD:$wd); 1168 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); 1169 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1170 // Note that binsxi and vselect treat the condition operand the opposite 1171 // way to each other. 1172 // (vselect cond, if_set, if_clear) 1173 // (BSEL_V cond, if_clear, if_set) 1174 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1175 ROWS:$wd_in))]; 1176 InstrItinClass Itinerary = itin; 1177 string Constraints = "$wd = $wd_in"; 1178 } 1179 1180 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1181 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1182 RegisterOperand ROWS = ROWD, 1183 InstrItinClass itin = NoItinerary> : 1184 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1185 1186 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1187 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1188 RegisterOperand ROWS = ROWD, 1189 InstrItinClass itin = NoItinerary> : 1190 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1191 1192 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1193 SplatComplexPattern SplatImm, 1194 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1195 InstrItinClass itin = NoItinerary> { 1196 dag OutOperandList = (outs ROWD:$wd); 1197 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1198 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1199 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1200 InstrItinClass Itinerary = itin; 1201 } 1202 1203 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1204 ValueType VecTy, Operand ImmOp, ImmLeaf Imm, 1205 RegisterOperand ROD, RegisterOperand ROWS, 1206 InstrItinClass itin = NoItinerary> { 1207 dag OutOperandList = (outs ROD:$rd); 1208 dag InOperandList = (ins ROWS:$ws, ImmOp:$n); 1209 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1210 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; 1211 InstrItinClass Itinerary = itin; 1212 } 1213 1214 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1215 RegisterOperand ROWD, RegisterOperand ROWS, 1216 Operand ImmOp, ImmLeaf Imm, 1217 InstrItinClass itin = NoItinerary> { 1218 dag OutOperandList = (outs ROWD:$wd); 1219 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); 1220 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1221 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1222 Imm:$n))]; 1223 string Constraints = "$wd = $wd_in"; 1224 InstrItinClass Itinerary = itin; 1225 } 1226 1227 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1228 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, 1229 RegisterClass RCWS> : 1230 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), 1231 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { 1232 bit usesCustomInserter = 1; 1233 } 1234 1235 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1236 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1237 RegisterOperand ROWS = ROWD, 1238 InstrItinClass itin = NoItinerary> { 1239 dag OutOperandList = (outs ROWD:$wd); 1240 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1241 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1242 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1243 InstrItinClass Itinerary = itin; 1244 } 1245 1246 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1247 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1248 RegisterOperand ROWS = ROWD, 1249 InstrItinClass itin = NoItinerary> { 1250 dag OutOperandList = (outs ROWD:$wd); 1251 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1252 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1253 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1254 InstrItinClass Itinerary = itin; 1255 } 1256 1257 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1258 RegisterOperand ROWS = ROWD, 1259 InstrItinClass itin = NoItinerary> { 1260 dag OutOperandList = (outs ROWD:$wd); 1261 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1262 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1263 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))]; 1264 InstrItinClass Itinerary = itin; 1265 } 1266 1267 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1268 InstrItinClass itin = NoItinerary> { 1269 dag OutOperandList = (outs ROWD:$wd); 1270 dag InOperandList = (ins vsplat_simm10:$s10); 1271 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1272 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1273 list<dag> Pattern = []; 1274 bit hasSideEffects = 0; 1275 InstrItinClass Itinerary = itin; 1276 } 1277 1278 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1279 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1280 InstrItinClass itin = NoItinerary> { 1281 dag OutOperandList = (outs ROWD:$wd); 1282 dag InOperandList = (ins ROWS:$ws); 1283 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1284 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1285 InstrItinClass Itinerary = itin; 1286 } 1287 1288 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1289 SDPatternOperator OpNode, RegisterOperand ROWD, 1290 RegisterOperand ROS = ROWD, 1291 InstrItinClass itin = NoItinerary> { 1292 dag OutOperandList = (outs ROWD:$wd); 1293 dag InOperandList = (ins ROS:$rs); 1294 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1295 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1296 InstrItinClass Itinerary = itin; 1297 } 1298 1299 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1300 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1301 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1302 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1303 let usesCustomInserter = 1; 1304 } 1305 1306 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1307 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1308 InstrItinClass itin = NoItinerary> { 1309 dag OutOperandList = (outs ROWD:$wd); 1310 dag InOperandList = (ins ROWS:$ws); 1311 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1312 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1313 InstrItinClass Itinerary = itin; 1314 } 1315 1316 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1317 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1318 RegisterOperand ROWT = ROWD, 1319 InstrItinClass itin = NoItinerary> { 1320 dag OutOperandList = (outs ROWD:$wd); 1321 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1322 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1323 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1324 InstrItinClass Itinerary = itin; 1325 } 1326 1327 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1328 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1329 RegisterOperand ROWT = ROWD, 1330 InstrItinClass itin = NoItinerary> { 1331 dag OutOperandList = (outs ROWD:$wd); 1332 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1333 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1334 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1335 ROWT:$wt))]; 1336 string Constraints = "$wd = $wd_in"; 1337 InstrItinClass Itinerary = itin; 1338 } 1339 1340 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1341 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1342 InstrItinClass itin = NoItinerary> { 1343 dag OutOperandList = (outs ROWD:$wd); 1344 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1345 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1346 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1347 InstrItinClass Itinerary = itin; 1348 } 1349 1350 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1351 RegisterOperand ROWS = ROWD, 1352 RegisterOperand ROWT = ROWD, 1353 InstrItinClass itin = NoItinerary> { 1354 dag OutOperandList = (outs ROWD:$wd); 1355 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1356 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1357 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1358 ROWT:$wt))]; 1359 string Constraints = "$wd = $wd_in"; 1360 InstrItinClass Itinerary = itin; 1361 } 1362 1363 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1364 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1365 InstrItinClass itin = NoItinerary> { 1366 dag OutOperandList = (outs ROWD:$wd); 1367 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1368 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1369 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1370 GPR32Opnd:$rt))]; 1371 InstrItinClass Itinerary = itin; 1372 string Constraints = "$wd = $wd_in"; 1373 } 1374 1375 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1376 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1377 RegisterOperand ROWT = ROWD, 1378 InstrItinClass itin = NoItinerary> { 1379 dag OutOperandList = (outs ROWD:$wd); 1380 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1381 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1382 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1383 ROWT:$wt))]; 1384 InstrItinClass Itinerary = itin; 1385 string Constraints = "$wd = $wd_in"; 1386 } 1387 1388 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1389 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1390 RegisterOperand ROWT = ROWD, 1391 InstrItinClass itin = NoItinerary> : 1392 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1393 1394 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1395 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1396 RegisterOperand ROWT = ROWD, 1397 InstrItinClass itin = NoItinerary> : 1398 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1399 1400 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1401 dag OutOperandList = (outs); 1402 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1403 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1404 list<dag> Pattern = []; 1405 InstrItinClass Itinerary = NoItinerary; 1406 bit isBranch = 1; 1407 bit isTerminator = 1; 1408 bit hasDelaySlot = 1; 1409 list<Register> Defs = [AT]; 1410 } 1411 1412 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1413 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1414 RegisterOperand ROS, 1415 InstrItinClass itin = NoItinerary> { 1416 dag OutOperandList = (outs ROWD:$wd); 1417 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); 1418 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1419 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; 1420 InstrItinClass Itinerary = itin; 1421 string Constraints = "$wd = $wd_in"; 1422 } 1423 1424 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1425 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1426 RegisterOperand ROFS> : 1427 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), 1428 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { 1429 bit usesCustomInserter = 1; 1430 string Constraints = "$wd = $wd_in"; 1431 } 1432 1433 class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1434 RegisterOperand ROWD, RegisterOperand ROFS, 1435 RegisterOperand ROIdx> : 1436 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), 1437 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1438 ROIdx:$n))]> { 1439 bit usesCustomInserter = 1; 1440 string Constraints = "$wd = $wd_in"; 1441 } 1442 1443 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1444 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1445 RegisterOperand ROWS = ROWD, 1446 InstrItinClass itin = NoItinerary> { 1447 dag OutOperandList = (outs ROWD:$wd); 1448 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); 1449 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1450 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1451 Imm:$n, 1452 ROWS:$ws, 1453 immz:$n2))]; 1454 InstrItinClass Itinerary = itin; 1455 string Constraints = "$wd = $wd_in"; 1456 } 1457 1458 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1459 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1460 RegisterOperand ROWT = ROWD, 1461 InstrItinClass itin = NoItinerary> { 1462 dag OutOperandList = (outs ROWD:$wd); 1463 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1464 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1465 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1466 InstrItinClass Itinerary = itin; 1467 } 1468 1469 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1470 RegisterOperand ROWD, 1471 RegisterOperand ROWS = ROWD, 1472 InstrItinClass itin = NoItinerary> { 1473 dag OutOperandList = (outs ROWD:$wd); 1474 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1475 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1476 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1477 ROWS:$ws))]; 1478 InstrItinClass Itinerary = itin; 1479 } 1480 1481 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1482 RegisterOperand ROWS = ROWD, 1483 RegisterOperand ROWT = ROWD> : 1484 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1485 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1486 1487 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1488 IsCommutable; 1489 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1490 IsCommutable; 1491 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1492 IsCommutable; 1493 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1494 IsCommutable; 1495 1496 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1497 MSA128BOpnd>, IsCommutable; 1498 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1499 MSA128HOpnd>, IsCommutable; 1500 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1501 MSA128WOpnd>, IsCommutable; 1502 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1503 MSA128DOpnd>, IsCommutable; 1504 1505 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1506 MSA128BOpnd>, IsCommutable; 1507 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1508 MSA128HOpnd>, IsCommutable; 1509 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1510 MSA128WOpnd>, IsCommutable; 1511 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1512 MSA128DOpnd>, IsCommutable; 1513 1514 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1515 MSA128BOpnd>, IsCommutable; 1516 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1517 MSA128HOpnd>, IsCommutable; 1518 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1519 MSA128WOpnd>, IsCommutable; 1520 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1521 MSA128DOpnd>, IsCommutable; 1522 1523 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1524 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1525 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1526 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1527 1528 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1529 MSA128BOpnd>; 1530 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1531 MSA128HOpnd>; 1532 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1533 MSA128WOpnd>; 1534 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1535 MSA128DOpnd>; 1536 1537 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1538 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1539 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1540 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1541 1542 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1543 MSA128BOpnd>; 1544 1545 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1546 MSA128BOpnd>; 1547 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1548 MSA128HOpnd>; 1549 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1550 MSA128WOpnd>; 1551 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1552 MSA128DOpnd>; 1553 1554 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1555 MSA128BOpnd>; 1556 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1557 MSA128HOpnd>; 1558 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1559 MSA128WOpnd>; 1560 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1561 MSA128DOpnd>; 1562 1563 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1564 IsCommutable; 1565 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1566 IsCommutable; 1567 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1568 IsCommutable; 1569 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1570 IsCommutable; 1571 1572 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1573 IsCommutable; 1574 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1575 IsCommutable; 1576 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1577 IsCommutable; 1578 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1579 IsCommutable; 1580 1581 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1582 MSA128BOpnd>, IsCommutable; 1583 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1584 MSA128HOpnd>, IsCommutable; 1585 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1586 MSA128WOpnd>, IsCommutable; 1587 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1588 MSA128DOpnd>, IsCommutable; 1589 1590 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1591 MSA128BOpnd>, IsCommutable; 1592 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1593 MSA128HOpnd>, IsCommutable; 1594 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1595 MSA128WOpnd>, IsCommutable; 1596 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1597 MSA128DOpnd>, IsCommutable; 1598 1599 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1600 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1601 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1602 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1603 1604 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1605 MSA128BOpnd>; 1606 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1607 MSA128HOpnd>; 1608 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1609 MSA128WOpnd>; 1610 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1611 MSA128DOpnd>; 1612 1613 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1614 MSA128BOpnd>; 1615 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1616 MSA128HOpnd>; 1617 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1618 MSA128WOpnd>; 1619 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1620 MSA128DOpnd>; 1621 1622 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; 1623 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; 1624 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; 1625 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; 1626 1627 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1628 MSA128BOpnd>; 1629 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1630 MSA128HOpnd>; 1631 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1632 MSA128WOpnd>; 1633 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1634 MSA128DOpnd>; 1635 1636 class BINSRI_B_DESC 1637 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, 1638 MSA128BOpnd>; 1639 class BINSRI_H_DESC 1640 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, 1641 MSA128HOpnd>; 1642 class BINSRI_W_DESC 1643 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, 1644 MSA128WOpnd>; 1645 class BINSRI_D_DESC 1646 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, 1647 MSA128DOpnd>; 1648 1649 class BMNZ_V_DESC { 1650 dag OutOperandList = (outs MSA128BOpnd:$wd); 1651 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1652 MSA128BOpnd:$wt); 1653 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1654 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1655 MSA128BOpnd:$ws, 1656 MSA128BOpnd:$wd_in))]; 1657 InstrItinClass Itinerary = NoItinerary; 1658 string Constraints = "$wd = $wd_in"; 1659 } 1660 1661 class BMNZI_B_DESC { 1662 dag OutOperandList = (outs MSA128BOpnd:$wd); 1663 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1664 vsplat_uimm8:$u8); 1665 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1666 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1667 MSA128BOpnd:$ws, 1668 MSA128BOpnd:$wd_in))]; 1669 InstrItinClass Itinerary = NoItinerary; 1670 string Constraints = "$wd = $wd_in"; 1671 } 1672 1673 class BMZ_V_DESC { 1674 dag OutOperandList = (outs MSA128BOpnd:$wd); 1675 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1676 MSA128BOpnd:$wt); 1677 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1678 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1679 MSA128BOpnd:$wd_in, 1680 MSA128BOpnd:$ws))]; 1681 InstrItinClass Itinerary = NoItinerary; 1682 string Constraints = "$wd = $wd_in"; 1683 } 1684 1685 class BMZI_B_DESC { 1686 dag OutOperandList = (outs MSA128BOpnd:$wd); 1687 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1688 vsplat_uimm8:$u8); 1689 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1690 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1691 MSA128BOpnd:$wd_in, 1692 MSA128BOpnd:$ws))]; 1693 InstrItinClass Itinerary = NoItinerary; 1694 string Constraints = "$wd = $wd_in"; 1695 } 1696 1697 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1698 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1699 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1700 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1701 1702 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1703 MSA128BOpnd>; 1704 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1705 MSA128HOpnd>; 1706 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1707 MSA128WOpnd>; 1708 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1709 MSA128DOpnd>; 1710 1711 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1712 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1713 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1714 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1715 1716 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1717 1718 class BSEL_V_DESC { 1719 dag OutOperandList = (outs MSA128BOpnd:$wd); 1720 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1721 MSA128BOpnd:$wt); 1722 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1723 // Note that vselect and BSEL_V treat the condition operand the opposite way 1724 // from each other. 1725 // (vselect cond, if_set, if_clear) 1726 // (BSEL_V cond, if_clear, if_set) 1727 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1728 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1729 MSA128BOpnd:$ws))]; 1730 InstrItinClass Itinerary = NoItinerary; 1731 string Constraints = "$wd = $wd_in"; 1732 } 1733 1734 class BSELI_B_DESC { 1735 dag OutOperandList = (outs MSA128BOpnd:$wd); 1736 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1737 vsplat_uimm8:$u8); 1738 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1739 // Note that vselect and BSEL_V treat the condition operand the opposite way 1740 // from each other. 1741 // (vselect cond, if_set, if_clear) 1742 // (BSEL_V cond, if_clear, if_set) 1743 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1744 vsplati8_uimm8:$u8, 1745 MSA128BOpnd:$ws))]; 1746 InstrItinClass Itinerary = NoItinerary; 1747 string Constraints = "$wd = $wd_in"; 1748 } 1749 1750 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1751 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1752 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1753 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1754 1755 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1756 MSA128BOpnd>; 1757 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1758 MSA128HOpnd>; 1759 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1760 MSA128WOpnd>; 1761 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1762 MSA128DOpnd>; 1763 1764 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1765 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1766 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1767 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1768 1769 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1770 1771 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1772 IsCommutable; 1773 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1774 IsCommutable; 1775 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1776 IsCommutable; 1777 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1778 IsCommutable; 1779 1780 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1781 MSA128BOpnd>; 1782 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1783 MSA128HOpnd>; 1784 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1785 MSA128WOpnd>; 1786 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1787 MSA128DOpnd>; 1788 1789 class CFCMSA_DESC { 1790 dag OutOperandList = (outs GPR32Opnd:$rd); 1791 dag InOperandList = (ins MSA128CROpnd:$cs); 1792 string AsmString = "cfcmsa\t$rd, $cs"; 1793 InstrItinClass Itinerary = NoItinerary; 1794 bit hasSideEffects = 1; 1795 } 1796 1797 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1798 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1799 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1800 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1801 1802 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1803 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1804 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1805 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1806 1807 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1808 vsplati8_simm5, MSA128BOpnd>; 1809 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1810 vsplati16_simm5, MSA128HOpnd>; 1811 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1812 vsplati32_simm5, MSA128WOpnd>; 1813 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1814 vsplati64_simm5, MSA128DOpnd>; 1815 1816 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1817 vsplati8_uimm5, MSA128BOpnd>; 1818 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1819 vsplati16_uimm5, MSA128HOpnd>; 1820 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1821 vsplati32_uimm5, MSA128WOpnd>; 1822 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1823 vsplati64_uimm5, MSA128DOpnd>; 1824 1825 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1826 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1827 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1828 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1829 1830 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1831 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1832 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1833 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1834 1835 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1836 vsplati8_simm5, MSA128BOpnd>; 1837 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1838 vsplati16_simm5, MSA128HOpnd>; 1839 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1840 vsplati32_simm5, MSA128WOpnd>; 1841 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1842 vsplati64_simm5, MSA128DOpnd>; 1843 1844 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1845 vsplati8_uimm5, MSA128BOpnd>; 1846 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1847 vsplati16_uimm5, MSA128HOpnd>; 1848 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1849 vsplati32_uimm5, MSA128WOpnd>; 1850 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1851 vsplati64_uimm5, MSA128DOpnd>; 1852 1853 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1854 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1855 MSA128BOpnd>; 1856 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1857 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1858 MSA128HOpnd>; 1859 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1860 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1861 MSA128WOpnd>; 1862 class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1863 uimm1_ptr, immZExt1Ptr, GPR64Opnd, 1864 MSA128DOpnd>; 1865 1866 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1867 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1868 MSA128BOpnd>; 1869 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1870 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1871 MSA128HOpnd>; 1872 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1873 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1874 MSA128WOpnd>; 1875 1876 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, 1877 uimm2_ptr, immZExt2Ptr, FGR32, 1878 MSA128W>; 1879 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, 1880 uimm1_ptr, immZExt1Ptr, FGR64, 1881 MSA128D>; 1882 1883 class CTCMSA_DESC { 1884 dag OutOperandList = (outs); 1885 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1886 string AsmString = "ctcmsa\t$cd, $rs"; 1887 InstrItinClass Itinerary = NoItinerary; 1888 bit hasSideEffects = 1; 1889 } 1890 1891 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1892 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1893 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1894 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1895 1896 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1897 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1898 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1899 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1900 1901 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1902 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1903 IsCommutable; 1904 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1905 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1906 IsCommutable; 1907 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1908 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1909 IsCommutable; 1910 1911 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1912 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1913 IsCommutable; 1914 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1915 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1916 IsCommutable; 1917 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1918 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1919 IsCommutable; 1920 1921 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1922 MSA128HOpnd, MSA128BOpnd, 1923 MSA128BOpnd>, IsCommutable; 1924 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1925 MSA128WOpnd, MSA128HOpnd, 1926 MSA128HOpnd>, IsCommutable; 1927 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1928 MSA128DOpnd, MSA128WOpnd, 1929 MSA128WOpnd>, IsCommutable; 1930 1931 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1932 MSA128HOpnd, MSA128BOpnd, 1933 MSA128BOpnd>, IsCommutable; 1934 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1935 MSA128WOpnd, MSA128HOpnd, 1936 MSA128HOpnd>, IsCommutable; 1937 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1938 MSA128DOpnd, MSA128WOpnd, 1939 MSA128WOpnd>, IsCommutable; 1940 1941 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1942 MSA128HOpnd, MSA128BOpnd, 1943 MSA128BOpnd>; 1944 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1945 MSA128WOpnd, MSA128HOpnd, 1946 MSA128HOpnd>; 1947 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1948 MSA128DOpnd, MSA128WOpnd, 1949 MSA128WOpnd>; 1950 1951 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 1952 MSA128HOpnd, MSA128BOpnd, 1953 MSA128BOpnd>; 1954 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 1955 MSA128WOpnd, MSA128HOpnd, 1956 MSA128HOpnd>; 1957 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 1958 MSA128DOpnd, MSA128WOpnd, 1959 MSA128WOpnd>; 1960 1961 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 1962 IsCommutable; 1963 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 1964 IsCommutable; 1965 1966 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 1967 IsCommutable; 1968 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 1969 IsCommutable; 1970 1971 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 1972 IsCommutable; 1973 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 1974 IsCommutable; 1975 1976 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 1977 MSA128WOpnd>; 1978 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 1979 MSA128DOpnd>; 1980 1981 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 1982 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 1983 1984 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 1985 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 1986 1987 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 1988 IsCommutable; 1989 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 1990 IsCommutable; 1991 1992 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 1993 IsCommutable; 1994 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 1995 IsCommutable; 1996 1997 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 1998 IsCommutable; 1999 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2000 IsCommutable; 2001 2002 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2003 IsCommutable; 2004 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2005 IsCommutable; 2006 2007 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2008 IsCommutable; 2009 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2010 IsCommutable; 2011 2012 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2013 IsCommutable; 2014 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2015 IsCommutable; 2016 2017 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2018 IsCommutable; 2019 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2020 IsCommutable; 2021 2022 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2023 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2024 2025 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2026 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2027 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2028 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2029 2030 // The fexp2.df instruction multiplies the first operand by 2 to the power of 2031 // the second operand. We therefore need a pseudo-insn in order to invent the 2032 // 1.0 when we only need to match ISD::FEXP2. 2033 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2034 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2035 let usesCustomInserter = 1 in { 2036 class FEXP2_W_1_PSEUDO_DESC : 2037 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2038 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2039 class FEXP2_D_1_PSEUDO_DESC : 2040 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2041 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2042 } 2043 2044 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2045 MSA128WOpnd, MSA128HOpnd>; 2046 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2047 MSA128DOpnd, MSA128WOpnd>; 2048 2049 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2050 MSA128WOpnd, MSA128HOpnd>; 2051 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2052 MSA128DOpnd, MSA128WOpnd>; 2053 2054 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2055 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2056 2057 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2058 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2059 2060 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2061 MSA128WOpnd, MSA128HOpnd>; 2062 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2063 MSA128DOpnd, MSA128WOpnd>; 2064 2065 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2066 MSA128WOpnd, MSA128HOpnd>; 2067 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2068 MSA128DOpnd, MSA128WOpnd>; 2069 2070 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2071 MSA128BOpnd, GPR32Opnd>; 2072 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2073 MSA128HOpnd, GPR32Opnd>; 2074 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2075 MSA128WOpnd, GPR32Opnd>; 2076 class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2077 MSA128DOpnd, GPR64Opnd>; 2078 2079 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2080 FGR32>; 2081 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2082 FGR64>; 2083 2084 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2085 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2086 2087 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2088 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2089 2090 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2091 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2092 2093 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2094 MSA128WOpnd>; 2095 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2096 MSA128DOpnd>; 2097 2098 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2099 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2100 2101 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2102 MSA128WOpnd>; 2103 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2104 MSA128DOpnd>; 2105 2106 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>; 2107 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>; 2108 2109 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2110 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2111 2112 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2113 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2114 2115 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2116 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2117 2118 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2119 MSA128WOpnd>; 2120 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2121 MSA128DOpnd>; 2122 2123 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2124 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2125 2126 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2127 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2128 2129 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2130 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2131 2132 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2133 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2134 2135 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2136 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2137 2138 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2139 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2140 2141 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2142 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2143 2144 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2145 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2146 2147 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2148 MSA128WOpnd>; 2149 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2150 MSA128DOpnd>; 2151 2152 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2153 MSA128WOpnd>; 2154 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2155 MSA128DOpnd>; 2156 2157 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2158 MSA128WOpnd>; 2159 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2160 MSA128DOpnd>; 2161 2162 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2163 MSA128WOpnd>; 2164 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2165 MSA128DOpnd>; 2166 2167 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2168 MSA128WOpnd>; 2169 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2170 MSA128DOpnd>; 2171 2172 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2173 MSA128WOpnd>; 2174 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2175 MSA128DOpnd>; 2176 2177 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2178 MSA128WOpnd>; 2179 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2180 MSA128DOpnd>; 2181 2182 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2183 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2184 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2185 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2186 2187 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2188 MSA128WOpnd>; 2189 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2190 MSA128DOpnd>; 2191 2192 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2193 MSA128WOpnd>; 2194 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2195 MSA128DOpnd>; 2196 2197 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2198 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2199 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2200 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2201 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2202 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2203 2204 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2205 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2206 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2207 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2208 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2209 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2210 2211 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2212 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2213 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2214 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2215 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2216 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2217 2218 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2219 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2220 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2221 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2222 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2223 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2224 2225 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2226 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2227 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2228 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2229 2230 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2231 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2232 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2233 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2234 2235 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2236 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2237 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2238 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2239 2240 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2241 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2242 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2243 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2244 2245 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, 2246 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; 2247 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, 2248 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; 2249 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, 2250 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; 2251 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, 2252 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; 2253 2254 class INSERT_B_VIDX_PSEUDO_DESC : 2255 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; 2256 class INSERT_H_VIDX_PSEUDO_DESC : 2257 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; 2258 class INSERT_W_VIDX_PSEUDO_DESC : 2259 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; 2260 class INSERT_D_VIDX_PSEUDO_DESC : 2261 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; 2262 2263 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2264 uimm2, immZExt2Ptr, 2265 MSA128WOpnd, FGR32Opnd>; 2266 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2267 uimm1, immZExt1Ptr, 2268 MSA128DOpnd, FGR64Opnd>; 2269 2270 class INSERT_FW_VIDX_PSEUDO_DESC : 2271 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; 2272 class INSERT_FD_VIDX_PSEUDO_DESC : 2273 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; 2274 2275 class INSERT_B_VIDX64_PSEUDO_DESC : 2276 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; 2277 class INSERT_H_VIDX64_PSEUDO_DESC : 2278 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; 2279 class INSERT_W_VIDX64_PSEUDO_DESC : 2280 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; 2281 class INSERT_D_VIDX64_PSEUDO_DESC : 2282 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; 2283 2284 class INSERT_FW_VIDX64_PSEUDO_DESC : 2285 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; 2286 class INSERT_FD_VIDX64_PSEUDO_DESC : 2287 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; 2288 2289 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, immZExt4, 2290 MSA128BOpnd>; 2291 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, immZExt3, 2292 MSA128HOpnd>; 2293 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, immZExt2, 2294 MSA128WOpnd>; 2295 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1, 2296 MSA128DOpnd>; 2297 2298 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2299 ValueType TyNode, RegisterOperand ROWD, 2300 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2301 InstrItinClass itin = NoItinerary> { 2302 dag OutOperandList = (outs ROWD:$wd); 2303 dag InOperandList = (ins MemOpnd:$addr); 2304 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2305 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2306 InstrItinClass Itinerary = itin; 2307 string DecoderMethod = "DecodeMSA128Mem"; 2308 } 2309 2310 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; 2311 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, mem_simm10_lsl1>; 2312 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, mem_simm10_lsl2>; 2313 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, mem_simm10_lsl3>; 2314 2315 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2316 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2317 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2318 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2319 2320 class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2321 InstrItinClass itin = NoItinerary> { 2322 dag OutOperandList = (outs RORD:$rd); 2323 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); 2324 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2325 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, 2326 (shl RORD:$rs, 2327 immZExt2Lsa:$sa)))]; 2328 InstrItinClass Itinerary = itin; 2329 } 2330 2331 class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>; 2332 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>; 2333 2334 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2335 MSA128HOpnd>; 2336 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2337 MSA128WOpnd>; 2338 2339 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2340 MSA128HOpnd>; 2341 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2342 MSA128WOpnd>; 2343 2344 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2345 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2346 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2347 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2348 2349 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2350 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2351 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2352 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2353 2354 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>; 2355 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>; 2356 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>; 2357 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>; 2358 2359 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>; 2360 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>; 2361 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>; 2362 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>; 2363 2364 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5, 2365 MSA128BOpnd>; 2366 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5, 2367 MSA128HOpnd>; 2368 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5, 2369 MSA128WOpnd>; 2370 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5, 2371 MSA128DOpnd>; 2372 2373 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5, 2374 MSA128BOpnd>; 2375 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5, 2376 MSA128HOpnd>; 2377 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5, 2378 MSA128WOpnd>; 2379 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5, 2380 MSA128DOpnd>; 2381 2382 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2383 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2384 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2385 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2386 2387 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>; 2388 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>; 2389 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>; 2390 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>; 2391 2392 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>; 2393 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>; 2394 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>; 2395 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>; 2396 2397 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5, 2398 MSA128BOpnd>; 2399 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5, 2400 MSA128HOpnd>; 2401 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5, 2402 MSA128WOpnd>; 2403 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5, 2404 MSA128DOpnd>; 2405 2406 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5, 2407 MSA128BOpnd>; 2408 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5, 2409 MSA128HOpnd>; 2410 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5, 2411 MSA128WOpnd>; 2412 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5, 2413 MSA128DOpnd>; 2414 2415 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2416 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2417 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2418 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2419 2420 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2421 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2422 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2423 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2424 2425 class MOVE_V_DESC { 2426 dag OutOperandList = (outs MSA128BOpnd:$wd); 2427 dag InOperandList = (ins MSA128BOpnd:$ws); 2428 string AsmString = "move.v\t$wd, $ws"; 2429 list<dag> Pattern = []; 2430 InstrItinClass Itinerary = NoItinerary; 2431 } 2432 2433 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2434 MSA128HOpnd>; 2435 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2436 MSA128WOpnd>; 2437 2438 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2439 MSA128HOpnd>; 2440 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2441 MSA128WOpnd>; 2442 2443 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2444 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2445 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2446 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2447 2448 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2449 MSA128HOpnd>; 2450 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2451 MSA128WOpnd>; 2452 2453 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2454 MSA128HOpnd>; 2455 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2456 MSA128WOpnd>; 2457 2458 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2459 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2460 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2461 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2462 2463 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2464 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2465 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2466 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2467 2468 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2469 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2470 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2471 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2472 2473 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2474 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2475 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2476 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2477 2478 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2479 MSA128BOpnd>; 2480 2481 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2482 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2483 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2484 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2485 2486 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2487 2488 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2489 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2490 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2491 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2492 2493 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2494 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2495 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2496 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2497 2498 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2499 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2500 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2501 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2502 2503 class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3, 2504 immZExt3, MSA128BOpnd>; 2505 class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4, 2506 immZExt4, MSA128HOpnd>; 2507 class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5, 2508 immZExt5, MSA128WOpnd>; 2509 class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6, 2510 immZExt6, MSA128DOpnd>; 2511 2512 class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3, 2513 immZExt3, MSA128BOpnd>; 2514 class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4, 2515 immZExt4, MSA128HOpnd>; 2516 class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5, 2517 immZExt5, MSA128WOpnd>; 2518 class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6, 2519 immZExt6, MSA128DOpnd>; 2520 2521 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2522 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2523 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2524 2525 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2526 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2527 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2528 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2529 2530 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2531 MSA128BOpnd, MSA128BOpnd, uimm4, 2532 immZExt4>; 2533 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2534 MSA128HOpnd, MSA128HOpnd, uimm3, 2535 immZExt3>; 2536 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2537 MSA128WOpnd, MSA128WOpnd, uimm2, 2538 immZExt2>; 2539 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2540 MSA128DOpnd, MSA128DOpnd, uimm1, 2541 immZExt1>; 2542 2543 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2544 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2545 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2546 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2547 2548 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2549 MSA128BOpnd>; 2550 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2551 MSA128HOpnd>; 2552 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2553 MSA128WOpnd>; 2554 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2555 MSA128DOpnd>; 2556 2557 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2558 MSA128BOpnd>; 2559 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2560 MSA128HOpnd>; 2561 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2562 MSA128WOpnd>; 2563 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2564 MSA128DOpnd>; 2565 2566 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2567 MSA128BOpnd>; 2568 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2569 MSA128HOpnd>; 2570 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2571 MSA128WOpnd>; 2572 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2573 MSA128DOpnd>; 2574 2575 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2576 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2577 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2578 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2579 2580 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2581 MSA128BOpnd>; 2582 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2583 MSA128HOpnd>; 2584 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2585 MSA128WOpnd>; 2586 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2587 MSA128DOpnd>; 2588 2589 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2590 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2591 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2592 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2593 2594 class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3, 2595 immZExt3, MSA128BOpnd>; 2596 class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4, 2597 immZExt4, MSA128HOpnd>; 2598 class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5, 2599 immZExt5, MSA128WOpnd>; 2600 class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6, 2601 immZExt6, MSA128DOpnd>; 2602 2603 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2604 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2605 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2606 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2607 2608 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2609 MSA128BOpnd>; 2610 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2611 MSA128HOpnd>; 2612 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2613 MSA128WOpnd>; 2614 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2615 MSA128DOpnd>; 2616 2617 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2618 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2619 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2620 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2621 2622 class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3, 2623 immZExt3, MSA128BOpnd>; 2624 class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4, 2625 immZExt4, MSA128HOpnd>; 2626 class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5, 2627 immZExt5, MSA128WOpnd>; 2628 class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, 2629 immZExt6, MSA128DOpnd>; 2630 2631 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2632 ValueType TyNode, RegisterOperand ROWD, 2633 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2634 InstrItinClass itin = NoItinerary> { 2635 dag OutOperandList = (outs); 2636 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2637 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2638 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2639 InstrItinClass Itinerary = itin; 2640 string DecoderMethod = "DecodeMSA128Mem"; 2641 } 2642 2643 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; 2644 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, mem_simm10_lsl1>; 2645 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, mem_simm10_lsl2>; 2646 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, mem_simm10_lsl3>; 2647 2648 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2649 MSA128BOpnd>; 2650 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2651 MSA128HOpnd>; 2652 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2653 MSA128WOpnd>; 2654 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2655 MSA128DOpnd>; 2656 2657 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2658 MSA128BOpnd>; 2659 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2660 MSA128HOpnd>; 2661 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2662 MSA128WOpnd>; 2663 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2664 MSA128DOpnd>; 2665 2666 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2667 MSA128BOpnd>; 2668 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2669 MSA128HOpnd>; 2670 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2671 MSA128WOpnd>; 2672 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2673 MSA128DOpnd>; 2674 2675 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2676 MSA128BOpnd>; 2677 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2678 MSA128HOpnd>; 2679 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2680 MSA128WOpnd>; 2681 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2682 MSA128DOpnd>; 2683 2684 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2685 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2686 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2687 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2688 2689 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2690 MSA128BOpnd>; 2691 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2692 MSA128HOpnd>; 2693 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2694 MSA128WOpnd>; 2695 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2696 MSA128DOpnd>; 2697 2698 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2699 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2700 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2701 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2702 2703 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2704 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2705 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2706 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2707 2708 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2709 MSA128BOpnd>; 2710 2711 // Instruction defs. 2712 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2713 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2714 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2715 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2716 2717 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2718 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2719 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2720 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2721 2722 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2723 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2724 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2725 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2726 2727 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2728 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2729 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2730 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2731 2732 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2733 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2734 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2735 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2736 2737 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2738 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2739 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2740 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2741 2742 def AND_V : AND_V_ENC, AND_V_DESC; 2743 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2744 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2745 MSA128BOpnd:$ws, 2746 MSA128BOpnd:$wt)>; 2747 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2748 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2749 MSA128BOpnd:$ws, 2750 MSA128BOpnd:$wt)>; 2751 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2752 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2753 MSA128BOpnd:$ws, 2754 MSA128BOpnd:$wt)>; 2755 2756 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2757 2758 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2759 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2760 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2761 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2762 2763 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2764 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2765 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2766 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2767 2768 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2769 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2770 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2771 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2772 2773 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2774 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2775 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2776 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2777 2778 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2779 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2780 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2781 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2782 2783 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2784 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2785 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2786 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2787 2788 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2789 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2790 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2791 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2792 2793 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2794 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2795 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2796 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2797 2798 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2799 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2800 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2801 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2802 2803 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2804 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2805 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2806 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2807 2808 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2809 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2810 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2811 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2812 2813 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2814 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2815 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2816 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2817 2818 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2819 2820 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2821 2822 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2823 2824 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2825 2826 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2827 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2828 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2829 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2830 2831 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2832 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2833 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2834 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2835 2836 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2837 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2838 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2839 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2840 2841 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2842 2843 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2844 2845 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2846 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2847 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2848 // Note that vselect and BSEL_V treat the condition operand the opposite way 2849 // from each other. 2850 // (vselect cond, if_set, if_clear) 2851 // (BSEL_V cond, if_clear, if_set) 2852 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2853 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2854 let Constraints = "$wd_in = $wd"; 2855 } 2856 2857 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2858 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2859 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2860 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2861 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2862 2863 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2864 2865 def BSET_B : BSET_B_ENC, BSET_B_DESC; 2866 def BSET_H : BSET_H_ENC, BSET_H_DESC; 2867 def BSET_W : BSET_W_ENC, BSET_W_DESC; 2868 def BSET_D : BSET_D_ENC, BSET_D_DESC; 2869 2870 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2871 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2872 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2873 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2874 2875 def BZ_B : BZ_B_ENC, BZ_B_DESC; 2876 def BZ_H : BZ_H_ENC, BZ_H_DESC; 2877 def BZ_W : BZ_W_ENC, BZ_W_DESC; 2878 def BZ_D : BZ_D_ENC, BZ_D_DESC; 2879 2880 def BZ_V : BZ_V_ENC, BZ_V_DESC; 2881 2882 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2883 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2884 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2885 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2886 2887 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2888 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2889 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2890 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2891 2892 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2893 2894 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2895 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2896 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2897 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2898 2899 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2900 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2901 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2902 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2903 2904 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2905 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2906 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2907 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2908 2909 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2910 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2911 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2912 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2913 2914 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2915 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2916 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2917 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2918 2919 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2920 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2921 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2922 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2923 2924 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2925 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2926 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2927 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2928 2929 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2930 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2931 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2932 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2933 2934 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2935 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2936 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2937 def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; 2938 2939 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2940 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2941 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64; 2942 2943 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2944 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2945 2946 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2947 2948 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2949 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2950 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2951 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2952 2953 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2954 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2955 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2956 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2957 2958 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2959 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2960 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2961 2962 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2963 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2964 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2965 2966 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2967 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 2968 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 2969 2970 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 2971 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 2972 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 2973 2974 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 2975 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 2976 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 2977 2978 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 2979 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 2980 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 2981 2982 def FADD_W : FADD_W_ENC, FADD_W_DESC; 2983 def FADD_D : FADD_D_ENC, FADD_D_DESC; 2984 2985 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 2986 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 2987 2988 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 2989 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 2990 2991 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 2992 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 2993 2994 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 2995 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 2996 2997 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 2998 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 2999 3000 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3001 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3002 3003 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3004 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3005 3006 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3007 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3008 3009 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3010 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3011 3012 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3013 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3014 3015 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3016 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3017 3018 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3019 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3020 3021 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3022 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3023 3024 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3025 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3026 3027 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3028 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3029 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3030 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3031 3032 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3033 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3034 3035 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3036 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3037 3038 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3039 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3040 3041 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3042 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3043 3044 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3045 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3046 3047 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3048 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3049 3050 def FILL_B : FILL_B_ENC, FILL_B_DESC; 3051 def FILL_H : FILL_H_ENC, FILL_H_DESC; 3052 def FILL_W : FILL_W_ENC, FILL_W_DESC; 3053 def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; 3054 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3055 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3056 3057 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3058 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3059 3060 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3061 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3062 3063 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3064 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3065 3066 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3067 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3068 3069 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3070 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3071 3072 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3073 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3074 3075 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3076 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3077 3078 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3079 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3080 3081 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3082 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3083 3084 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3085 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3086 3087 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3088 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3089 3090 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3091 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3092 3093 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3094 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3095 3096 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3097 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3098 3099 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3100 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3101 3102 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3103 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3104 3105 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3106 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3107 3108 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3109 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3110 3111 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3112 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3113 3114 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3115 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3116 3117 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3118 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3119 3120 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3121 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3122 3123 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3124 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3125 3126 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3127 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3128 3129 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3130 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3131 3132 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3133 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3134 3135 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3136 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3137 3138 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3139 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3140 3141 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3142 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3143 3144 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3145 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3146 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3147 3148 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3149 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3150 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3151 3152 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3153 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3154 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3155 3156 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3157 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3158 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3159 3160 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3161 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3162 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3163 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3164 3165 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3166 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3167 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3168 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3169 3170 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3171 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3172 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3173 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3174 3175 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3176 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3177 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3178 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3179 3180 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3181 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3182 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3183 def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; 3184 3185 // INSERT_FW_PSEUDO defined after INSVE_W 3186 // INSERT_FD_PSEUDO defined after INSVE_D 3187 3188 // There is a fourth operand that is not present in the encoding. Use a 3189 // custom decoder to get a chance to add it. 3190 let DecoderMethod = "DecodeINSVE_DF" in { 3191 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3192 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3193 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3194 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3195 } 3196 3197 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3198 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3199 3200 def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3201 def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3202 def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3203 def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3204 def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3205 def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3206 3207 def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; 3208 def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; 3209 def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; 3210 def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; 3211 def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; 3212 def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; 3213 3214 def LD_B: LD_B_ENC, LD_B_DESC; 3215 def LD_H: LD_H_ENC, LD_H_DESC; 3216 def LD_W: LD_W_ENC, LD_W_DESC; 3217 def LD_D: LD_D_ENC, LD_D_DESC; 3218 3219 def LDI_B : LDI_B_ENC, LDI_B_DESC; 3220 def LDI_H : LDI_H_ENC, LDI_H_DESC; 3221 def LDI_W : LDI_W_ENC, LDI_W_DESC; 3222 def LDI_D : LDI_D_ENC, LDI_D_DESC; 3223 3224 def LSA : LSA_ENC, LSA_DESC; 3225 def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; 3226 3227 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3228 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3229 3230 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3231 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3232 3233 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3234 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3235 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3236 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3237 3238 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3239 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3240 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3241 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3242 3243 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3244 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3245 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3246 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3247 3248 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3249 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3250 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3251 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3252 3253 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3254 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3255 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3256 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3257 3258 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3259 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3260 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3261 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3262 3263 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3264 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3265 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3266 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3267 3268 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3269 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3270 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3271 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3272 3273 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3274 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3275 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3276 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3277 3278 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3279 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3280 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3281 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3282 3283 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3284 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3285 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3286 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3287 3288 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3289 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3290 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3291 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3292 3293 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3294 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3295 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3296 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3297 3298 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3299 3300 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3301 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3302 3303 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3304 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3305 3306 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3307 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3308 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3309 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3310 3311 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3312 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3313 3314 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3315 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3316 3317 def MULV_B : MULV_B_ENC, MULV_B_DESC; 3318 def MULV_H : MULV_H_ENC, MULV_H_DESC; 3319 def MULV_W : MULV_W_ENC, MULV_W_DESC; 3320 def MULV_D : MULV_D_ENC, MULV_D_DESC; 3321 3322 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3323 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3324 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3325 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3326 3327 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3328 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3329 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3330 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3331 3332 def NOR_V : NOR_V_ENC, NOR_V_DESC; 3333 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3334 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3335 MSA128BOpnd:$ws, 3336 MSA128BOpnd:$wt)>; 3337 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3338 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3339 MSA128BOpnd:$ws, 3340 MSA128BOpnd:$wt)>; 3341 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3342 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3343 MSA128BOpnd:$ws, 3344 MSA128BOpnd:$wt)>; 3345 3346 def NORI_B : NORI_B_ENC, NORI_B_DESC; 3347 3348 def OR_V : OR_V_ENC, OR_V_DESC; 3349 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3350 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3351 MSA128BOpnd:$ws, 3352 MSA128BOpnd:$wt)>; 3353 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3354 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3355 MSA128BOpnd:$ws, 3356 MSA128BOpnd:$wt)>; 3357 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3358 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3359 MSA128BOpnd:$ws, 3360 MSA128BOpnd:$wt)>; 3361 3362 def ORI_B : ORI_B_ENC, ORI_B_DESC; 3363 3364 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3365 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3366 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3367 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3368 3369 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3370 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3371 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3372 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3373 3374 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3375 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3376 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3377 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3378 3379 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3380 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3381 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3382 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3383 3384 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3385 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3386 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3387 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3388 3389 def SHF_B : SHF_B_ENC, SHF_B_DESC; 3390 def SHF_H : SHF_H_ENC, SHF_H_DESC; 3391 def SHF_W : SHF_W_ENC, SHF_W_DESC; 3392 3393 def SLD_B : SLD_B_ENC, SLD_B_DESC; 3394 def SLD_H : SLD_H_ENC, SLD_H_DESC; 3395 def SLD_W : SLD_W_ENC, SLD_W_DESC; 3396 def SLD_D : SLD_D_ENC, SLD_D_DESC; 3397 3398 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3399 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3400 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3401 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3402 3403 def SLL_B : SLL_B_ENC, SLL_B_DESC; 3404 def SLL_H : SLL_H_ENC, SLL_H_DESC; 3405 def SLL_W : SLL_W_ENC, SLL_W_DESC; 3406 def SLL_D : SLL_D_ENC, SLL_D_DESC; 3407 3408 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3409 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3410 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3411 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3412 3413 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3414 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3415 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3416 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3417 3418 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3419 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3420 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3421 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3422 3423 def SRA_B : SRA_B_ENC, SRA_B_DESC; 3424 def SRA_H : SRA_H_ENC, SRA_H_DESC; 3425 def SRA_W : SRA_W_ENC, SRA_W_DESC; 3426 def SRA_D : SRA_D_ENC, SRA_D_DESC; 3427 3428 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3429 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3430 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3431 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3432 3433 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3434 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3435 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3436 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3437 3438 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3439 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3440 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3441 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3442 3443 def SRL_B : SRL_B_ENC, SRL_B_DESC; 3444 def SRL_H : SRL_H_ENC, SRL_H_DESC; 3445 def SRL_W : SRL_W_ENC, SRL_W_DESC; 3446 def SRL_D : SRL_D_ENC, SRL_D_DESC; 3447 3448 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3449 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3450 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3451 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3452 3453 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3454 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3455 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3456 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3457 3458 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3459 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3460 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3461 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3462 3463 def ST_B: ST_B_ENC, ST_B_DESC; 3464 def ST_H: ST_H_ENC, ST_H_DESC; 3465 def ST_W: ST_W_ENC, ST_W_DESC; 3466 def ST_D: ST_D_ENC, ST_D_DESC; 3467 3468 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3469 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3470 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3471 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3472 3473 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3474 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3475 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3476 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3477 3478 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3479 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3480 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3481 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3482 3483 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3484 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3485 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3486 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3487 3488 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3489 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3490 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3491 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3492 3493 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3494 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3495 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3496 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3497 3498 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3499 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3500 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3501 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3502 3503 def XOR_V : XOR_V_ENC, XOR_V_DESC; 3504 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3505 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3506 MSA128BOpnd:$ws, 3507 MSA128BOpnd:$wt)>; 3508 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3509 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3510 MSA128BOpnd:$ws, 3511 MSA128BOpnd:$wt)>; 3512 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3513 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3514 MSA128BOpnd:$ws, 3515 MSA128BOpnd:$wt)>; 3516 3517 def XORI_B : XORI_B_ENC, XORI_B_DESC; 3518 3519 // Patterns. 3520 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3521 Pat<pattern, result>, Requires<pred>; 3522 3523 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3524 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3525 3526 def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>; 3527 def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>; 3528 def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>; 3529 3530 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr), 3531 (ST_H MSA128H:$ws, addrimm10:$addr)>; 3532 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr), 3533 (ST_W MSA128W:$ws, addrimm10:$addr)>; 3534 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr), 3535 (ST_D MSA128D:$ws, addrimm10:$addr)>; 3536 3537 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3538 RegisterOperand ROWS = ROWD, 3539 InstrItinClass itin = NoItinerary> : 3540 MSAPseudo<(outs ROWD:$wd), 3541 (ins ROWS:$ws), 3542 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3543 InstrItinClass Itinerary = itin; 3544 } 3545 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3546 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3547 MSA128WOpnd:$ws)>; 3548 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3549 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3550 MSA128DOpnd:$ws)>; 3551 3552 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3553 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3554 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3555 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3556 3557 // These are endian-independent because the element size doesnt change 3558 def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3559 def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3560 def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3561 def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3562 def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3563 def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3564 3565 // Little endian bitcasts are always no-ops 3566 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3567 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3568 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3569 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3570 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3571 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3572 3573 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3574 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3575 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3576 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3577 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3578 3579 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3580 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3581 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3582 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3583 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3584 3585 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3586 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3587 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3588 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3589 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3590 3591 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3592 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3593 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3594 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3595 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3596 3597 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3598 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3599 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3600 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3601 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3602 3603 // Big endian bitcasts expand to shuffle instructions. 3604 // This is because bitcast is defined to be a store/load sequence and the 3605 // vector store/load instructions are mixed-endian with respect to the vector 3606 // as a whole (little endian with respect to element order, but big endian 3607 // elements). 3608 3609 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3610 RegisterClass DstRC, MSAInst Insn, 3611 RegisterClass ViaRC> : 3612 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3613 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3614 DstRC), 3615 [HasMSA, IsBE]>; 3616 3617 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3618 RegisterClass DstRC, MSAInst Insn, 3619 RegisterClass ViaRC> : 3620 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3621 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3622 DstRC), 3623 [HasMSA, IsBE]>; 3624 3625 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3626 RegisterClass DstRC> : 3627 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3628 3629 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3630 RegisterClass DstRC> : 3631 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3632 3633 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3634 RegisterClass DstRC> : 3635 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3636 (COPY_TO_REGCLASS 3637 (SHF_W 3638 (COPY_TO_REGCLASS 3639 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3640 MSA128W), 177), 3641 DstRC), 3642 [HasMSA, IsBE]>; 3643 3644 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3645 RegisterClass DstRC> : 3646 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3647 3648 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3649 RegisterClass DstRC> : 3650 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3651 3652 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3653 RegisterClass DstRC> : 3654 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3655 3656 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3657 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3658 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3659 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3660 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3661 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3662 3663 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3664 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3665 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3666 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3667 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3668 3669 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3670 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3671 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3672 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3673 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3674 3675 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3676 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3677 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3678 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3679 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3680 3681 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3682 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3683 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3684 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3685 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3686 3687 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3688 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3689 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3690 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3691 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3692 3693 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3694 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3695 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3696 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3697 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3698 3699 // Pseudos used to implement BNZ.df, and BZ.df 3700 3701 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3702 RegisterClass RCWS, 3703 InstrItinClass itin = NoItinerary> : 3704 MipsPseudo<(outs GPR32:$dst), 3705 (ins RCWS:$ws), 3706 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3707 bit usesCustomInserter = 1; 3708 } 3709 3710 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3711 MSA128B, NoItinerary>; 3712 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3713 MSA128H, NoItinerary>; 3714 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3715 MSA128W, NoItinerary>; 3716 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3717 MSA128D, NoItinerary>; 3718 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3719 MSA128B, NoItinerary>; 3720 3721 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3722 MSA128B, NoItinerary>; 3723 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3724 MSA128H, NoItinerary>; 3725 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3726 MSA128W, NoItinerary>; 3727 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3728 MSA128D, NoItinerary>; 3729 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3730 MSA128B, NoItinerary>; 3731 3732 // Vector extraction with fixed index. 3733 // 3734 // Extracting 32-bit values on MSA32 should always use COPY_S_W rather than 3735 // COPY_U_W, even for the zero-extended case. This is because our forward 3736 // compatibility strategy is to consider registers to be infinitely 3737 // sign-extended so that a MIPS64 can execute MIPS32 code without getting 3738 // different register values. 3739 def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx), 3740 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3741 def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx), 3742 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3743 3744 // Extracting 64-bit values on MSA64 should always use COPY_S_D rather than 3745 // COPY_U_D, even for the zero-extended case. This is because our forward 3746 // compatibility strategy is to consider registers to be infinitely 3747 // sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64 3748 // code without getting different register values. 3749 def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx), 3750 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3751 def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx), 3752 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3753 3754 // Vector extraction with variable index 3755 def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3756 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3757 i32:$idx), 3758 sub_lo)), 3759 GPR32), (i32 24))>; 3760 def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3761 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3762 i32:$idx), 3763 sub_lo)), 3764 GPR32), (i32 16))>; 3765 def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3766 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3767 i32:$idx), 3768 sub_lo)), 3769 GPR32)>; 3770 def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3771 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3772 i32:$idx), 3773 sub_64)), 3774 GPR64), [HasMSA, IsGP64bit]>; 3775 3776 def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3777 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3778 i32:$idx), 3779 sub_lo)), 3780 GPR32), (i32 24))>; 3781 def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3782 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3783 i32:$idx), 3784 sub_lo)), 3785 GPR32), (i32 16))>; 3786 def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3787 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3788 i32:$idx), 3789 sub_lo)), 3790 GPR32)>; 3791 def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3792 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3793 i32:$idx), 3794 sub_64)), 3795 GPR64), [HasMSA, IsGP64bit]>; 3796 3797 def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3798 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3799 i32:$idx), 3800 sub_lo))>; 3801 def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3802 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3803 i32:$idx), 3804 sub_64))>; 3805 3806 // Vector extraction with variable index (N64 ABI) 3807 def : MSAPat< 3808 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), 3809 (SRA (COPY_TO_REGCLASS 3810 (i32 (EXTRACT_SUBREG 3811 (SPLAT_B v16i8:$ws, 3812 (COPY_TO_REGCLASS 3813 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3814 sub_lo)), 3815 GPR32), 3816 (i32 24))>; 3817 def : MSAPat< 3818 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), 3819 (SRA (COPY_TO_REGCLASS 3820 (i32 (EXTRACT_SUBREG 3821 (SPLAT_H v8i16:$ws, 3822 (COPY_TO_REGCLASS 3823 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3824 sub_lo)), 3825 GPR32), 3826 (i32 16))>; 3827 def : MSAPat< 3828 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), 3829 (COPY_TO_REGCLASS 3830 (i32 (EXTRACT_SUBREG 3831 (SPLAT_W v4i32:$ws, 3832 (COPY_TO_REGCLASS 3833 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3834 sub_lo)), 3835 GPR32)>; 3836 def : MSAPat< 3837 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), 3838 (COPY_TO_REGCLASS 3839 (i64 (EXTRACT_SUBREG 3840 (SPLAT_D v2i64:$ws, 3841 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3842 sub_64)), 3843 GPR64), [HasMSA, IsGP64bit]>; 3844 3845 def : MSAPat< 3846 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), 3847 (SRL (COPY_TO_REGCLASS 3848 (i32 (EXTRACT_SUBREG 3849 (SPLAT_B v16i8:$ws, 3850 (COPY_TO_REGCLASS 3851 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3852 sub_lo)), 3853 GPR32), 3854 (i32 24))>; 3855 def : MSAPat< 3856 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), 3857 (SRL (COPY_TO_REGCLASS 3858 (i32 (EXTRACT_SUBREG 3859 (SPLAT_H v8i16:$ws, 3860 (COPY_TO_REGCLASS 3861 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3862 sub_lo)), 3863 GPR32), 3864 (i32 16))>; 3865 def : MSAPat< 3866 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), 3867 (COPY_TO_REGCLASS 3868 (i32 (EXTRACT_SUBREG 3869 (SPLAT_W v4i32:$ws, 3870 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3871 sub_lo)), 3872 GPR32)>; 3873 def : MSAPat< 3874 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), 3875 (COPY_TO_REGCLASS 3876 (i64 (EXTRACT_SUBREG 3877 (SPLAT_D v2i64:$ws, 3878 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3879 sub_64)), 3880 GPR64), 3881 [HasMSA, IsGP64bit]>; 3882 3883 def : MSAPat< 3884 (f32 (vector_extract v4f32:$ws, i64:$idx)), 3885 (f32 (EXTRACT_SUBREG 3886 (SPLAT_W v4f32:$ws, 3887 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3888 sub_lo))>; 3889 def : MSAPat< 3890 (f64 (vector_extract v2f64:$ws, i64:$idx)), 3891 (f64 (EXTRACT_SUBREG 3892 (SPLAT_D v2f64:$ws, 3893 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3894 sub_64))>; 3895
