1 //===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 // Primary reference: 11 // A2 Processor User's Manual. 12 // IBM (as updated in) 2010. 13 14 //===----------------------------------------------------------------------===// 15 // Functional units on the PowerPC A2 chip sets 16 // 17 def A2_XU : FuncUnit; // A2_XU pipeline 18 def A2_FU : FuncUnit; // FI pipeline 19 20 // 21 // This file defines the itinerary class data for the PPC A2 processor. 22 // 23 //===----------------------------------------------------------------------===// 24 25 26 def PPCA2Itineraries : ProcessorItineraries< 27 [A2_XU, A2_FU], [], [ 28 InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>], 29 [1, 0, 0]>, 30 InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>], 31 [2, 0, 0]>, 32 InstrItinData<IIC_IntISEL, [InstrStage<1, [A2_XU]>], 33 [2, 0, 0, 0]>, 34 InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>], 35 [2, 0, 0]>, 36 InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>], 37 [39, 0, 0]>, 38 InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>], 39 [71, 0, 0]>, 40 InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>], 41 [5, 0, 0]>, 42 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>], 43 [5, 0, 0]>, 44 InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>], 45 [6, 0, 0]>, 46 InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>], 47 [2, 0, 0]>, 48 InstrItinData<IIC_IntRotateD, [InstrStage<1, [A2_XU]>], 49 [2, 0, 0]>, 50 InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>], 51 [2, 0, 0]>, 52 InstrItinData<IIC_IntShift, [InstrStage<1, [A2_XU]>], 53 [2, 0, 0]>, 54 InstrItinData<IIC_IntTrapW, [InstrStage<1, [A2_XU]>], 55 [2, 0]>, 56 InstrItinData<IIC_IntTrapD, [InstrStage<1, [A2_XU]>], 57 [2, 0]>, 58 InstrItinData<IIC_BrB, [InstrStage<1, [A2_XU]>], 59 [6, 0, 0]>, 60 InstrItinData<IIC_BrCR, [InstrStage<1, [A2_XU]>], 61 [1, 0, 0]>, 62 InstrItinData<IIC_BrMCR, [InstrStage<1, [A2_XU]>], 63 [5, 0, 0]>, 64 InstrItinData<IIC_BrMCRX, [InstrStage<1, [A2_XU]>], 65 [1, 0, 0]>, 66 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [A2_XU]>], 67 [1, 0, 0]>, 68 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [A2_XU]>], 69 [1, 0, 0]>, 70 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [A2_XU]>], 71 [1, 0, 0]>, 72 InstrItinData<IIC_LdStLoad, [InstrStage<1, [A2_XU]>], 73 [6, 0, 0]>, 74 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>], 75 [6, 8, 0, 0]>, 76 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [A2_XU]>], 77 [6, 8, 0, 0]>, 78 InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>], 79 [6, 0, 0]>, 80 InstrItinData<IIC_LdStLDUX, [InstrStage<1, [A2_XU]>], 81 [6, 0, 0]>, 82 InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>], 83 [0, 0, 0]>, 84 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>], 85 [2, 0, 0, 0]>, 86 InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>], 87 [16, 0, 0]>, 88 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>], 89 [0, 0, 0]>, 90 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>], 91 [2, 0, 0, 0]>, 92 InstrItinData<IIC_LdStLFD, [InstrStage<1, [A2_XU]>], 93 [7, 0, 0]>, 94 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>], 95 [7, 9, 0, 0]>, 96 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [A2_XU]>], 97 [7, 9, 0, 0]>, 98 InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>], 99 [6, 0, 0]>, 100 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>], 101 [6, 8, 0, 0]>, 102 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [A2_XU]>], 103 [6, 8, 0, 0]>, 104 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>], 105 [82, 0, 0]>, // L2 latency 106 InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>], 107 [0, 0, 0]>, 108 InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>], 109 [2, 0, 0, 0]>, 110 InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [A2_XU]>], 111 [2, 0, 0, 0]>, 112 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>], 113 [82, 0, 0]>, // L2 latency 114 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>], 115 [82, 0, 0]>, // L2 latency 116 InstrItinData<IIC_LdStSync, [InstrStage<1, [A2_XU]>], 117 [6]>, 118 InstrItinData<IIC_SprISYNC, [InstrStage<1, [A2_XU]>], 119 [16]>, 120 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [A2_XU]>], 121 [16, 0]>, 122 InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>], 123 [6, 0]>, 124 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [A2_XU]>], 125 [1, 0]>, 126 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>], 127 [4, 0]>, 128 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>], 129 [6, 0]>, 130 InstrItinData<IIC_SprMFTB, [InstrStage<1, [A2_XU]>], 131 [4, 0]>, 132 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [A2_XU]>], 133 [6, 0]>, 134 InstrItinData<IIC_SprRFI, [InstrStage<1, [A2_XU]>], 135 [16]>, 136 InstrItinData<IIC_SprSC, [InstrStage<1, [A2_XU]>], 137 [16]>, 138 InstrItinData<IIC_FPGeneral, [InstrStage<1, [A2_FU]>], 139 [6, 0, 0]>, 140 InstrItinData<IIC_FPAddSub, [InstrStage<1, [A2_FU]>], 141 [6, 0, 0]>, 142 InstrItinData<IIC_FPCompare, [InstrStage<1, [A2_FU]>], 143 [5, 0, 0]>, 144 InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>], 145 [72, 0, 0]>, 146 InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>], 147 [59, 0, 0]>, 148 InstrItinData<IIC_FPSqrtD, [InstrStage<1, [A2_FU]>], 149 [69, 0, 0]>, 150 InstrItinData<IIC_FPSqrtS, [InstrStage<1, [A2_FU]>], 151 [65, 0, 0]>, 152 InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>], 153 [6, 0, 0, 0]>, 154 InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>], 155 [6, 0]> 156 ]>; 157 158 // ===---------------------------------------------------------------------===// 159 // A2 machine model for scheduling and other instruction cost heuristics. 160 161 def PPCA2Model : SchedMachineModel { 162 let IssueWidth = 1; // 1 instruction is dispatched per cycle. 163 let LoadLatency = 6; // Optimistic load latency assuming bypass. 164 // This is overriden by OperandCycles if the 165 // Itineraries are queried instead. 166 let MispredictPenalty = 13; 167 168 let CompleteModel = 0; 169 170 let Itineraries = PPCA2Itineraries; 171 } 172 173
