1 ; REQUIRES: asserts 2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s 3 ; 4 ; Test for bug in misched memory dependency calculation. 5 ; 6 ; CHECK: ********** MI Scheduling ********** 7 ; CHECK: misched_bug:BB#0 entry 8 ; CHECK: SU(2): %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0 9 ; CHECK: Successors: 10 ; CHECK-NEXT: val SU(5): Latency=4 Reg=%vreg2 11 ; CHECK-NEXT: ch SU(4): Latency=0 12 ; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 13 ; CHECK: Successors: 14 ; CHECK: ch SU(4): Latency=0 15 ; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 16 ; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2 17 ; CHECK: ** ScheduleDAGMI::schedule picking next node 18 define i32 @misched_bug(i32* %ptr1, i32* %ptr2) { 19 entry: 20 %ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1 21 %val1 = load i32, i32* %ptr1_plus1, align 4 22 store i32 0, i32* %ptr1, align 4 23 store i32 0, i32* %ptr2, align 4 24 ret i32 %val1 25 } 26
